Abstract: Position controlled waveguides and methods of manufacturing the same are disclosed. An example apparatus includes a substrate with a channel that extends into a first surface of the substrate to a second surface of the substrate, wherein the second surface is recessed relative to the first surface; buffer material having a first index of refraction on the second surface of the substrate; and a waveguide on the buffer material, the waveguide having a second index of refraction that is higher than the first index of refraction.

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

Abstract: Methods, systems, apparatus, and articles of manufacture to produce nano-roughened integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a substrate, a semiconductor die, and a metal interconnect to electrically couple the semiconductor die to the substrate, the metal interconnect including a nano-roughened surface.

Abstract: Methods and apparatus to increase glass core thickness are disclosed. An example apparatus includes a first glass substrate, a second glass substrate, an interface layer between the first glass substrate and the second glass substrate, the interface layer coupling the first glass substrate to the second glass substrate, and an interconnect extending through at least a portion of the first glass substrate and at least a portion of the second glass substrate.

Abstract: A substrate of a microelectronic assembly is provided, the substrate comprising conductive traces through an organic dielectric, and a coating comprising silicon and oxygen. The substrate is configured to couple with a component electrically and mechanically by at least one or more conductive via through the coating, the conductive via being electrically connected to the conductive traces, such that the coating is between the organic dielectric and the component when coupled. In some embodiments, the component includes another coating comprising silicon and oxygen, with conductive vias through the second coating. The conductive vias and the coating of the substrate are configured to bind with the conductive vias and the coating of the component respectively to form hybrid bonds.

Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Abstract: Embodiments may relate to a semiconductor package that includes a routing trace coupled with a substrate. The routing trace may be linear on a side of the routing trace between the substrate and a top of the routing trace. The semiconductor package may further include a power trace coupled with the substrate. The power trace may be concave on a side of the power trace between the substrate and a top of the power trace. Other embodiments may be described and/or claimed.

Abstract: Disclosed herein are high-permeability magnetic thin films for coaxial metal inductor loop structures formed in through glass vias of a glass core package substrate, and related methods, devices, and systems. Exemplary coaxial metal inductor loop structures include a high-permeability magnetic layer within and on a surface of a through glass via extending through the glass core package substrate and a conductive layer on the high-permeability magnetic layer.

Abstract: An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

Abstract: An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

Abstract: Embodiments include one or more air core inductors (ACIs) and a method of forming the ACIs. The ACI includes a first inductor loop on a substrate. The first inductor loop has a first line and a second line. The first line has a first thickness that is greater than a second thickness of the second line. The ACI also includes a dielectric over the substrate and the first and second lines. The first line has a top surface above a top surface of the second line. The ACI further includes a second inductor loop on the dielectric and the first inductor loop. The second inductor loop has is coupled to the top surface of the first line of the first inductor loop. The first inductor loop may also have a third thickness, where the third thickness is the distance between the top surfaces of the first and second line.

Abstract: An integrated circuit device, comprising a substrate comprising a dielectric material and a conductor on or within the dielectric material of the substrate. The conductor comprises a first portion comprising a first sloped sidewall, wherein a first base width of the first portion is greater than a first top width of the first portion. The conductor also comprises a second portion over the first portion, the second portion comprising a second sloped sidewall, wherein a second base width of the upper portion is greater than both a second top width of the second portion and the first top width of the first portion.

Abstract: Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.