Patents by Inventor Jerome Ciavatti

Jerome Ciavatti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10644149
    Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a laterally-diffused metal-oxide-semiconductor device. A fin projects from a substrate, a channel region and a drain extension are arranged in a first section of the fin and the substrate beneath the first section of the fin, a source region is arranged in the first section of the fin, a drain region is arranged in a second section of the fin and the substrate beneath the second section of the fin, and a gate structure is arranged over the channel region. The drain region and the source region have an opposite conductivity type from the channel region. A trench isolation region is arranged in the fin between the first section of the fin and the second section of the fin. A dummy gate is arranged over a portion of the second section of the fin.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Jerome Ciavatti
  • Publication number: 20200135917
    Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a laterally-diffused metal-oxide-semiconductor device. A fin projects from a substrate, a channel region and a drain extension are arranged in a first section of the fin and the substrate beneath the first section of the fin, a source region is arranged in the first section of the fin, a drain region is arranged in a second section of the fin and the substrate beneath the second section of the fin, and a gate structure is arranged over the channel region. The drain region and the source region have an opposite conductivity type from the channel region. A trench isolation region is arranged in the fin between the first section of the fin and the second section of the fin. A dummy gate is arranged over a portion of the second section of the fin.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Jagar Singh, Jerome Ciavatti
  • Patent number: 10636894
    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
  • Patent number: 10593754
    Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Jerome Ciavatti, Jae Gon Lee, Josef Watts
  • Publication number: 20200035785
    Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 30, 2020
    Inventors: Jagar Singh, Jerome Ciavatti, Jae Gon Lee, Josef Watts
  • Patent number: 10475890
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu, Scott Beasor, Erik Geiss, Jerome Ciavatti, Jae Gon Lee
  • Patent number: 10418365
    Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti, Rinus Tek Po Lee
  • Publication number: 20190280105
    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
  • Patent number: 10410929
    Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jianwei Peng, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie
  • Patent number: 10373877
    Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Haiting Wang, Hong Yu, Hui Zang, Wei Zhao, Yue Zhong, Guowei Xu, Laertis Economikos, Jerome Ciavatti, Scott Beasor
  • Publication number: 20190206743
    Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 4, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui ZANG, Jianwei PENG, Yi QI, Hsien-Ching LO, Jerome CIAVATTI, Ruilong XIE
  • Patent number: 10290712
    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A body region is arranged partially in the substrate and partially in the first fin. A drain region is arranged partially in the substrate, partially in the first fin, and partially in the second fin. The body and drain regions respectively have opposite first and second conductivity types. A source region of the second conductivity type is located within the first well in the first fin, and a gate structure is arranged to overlap with a portion of the first fin. The first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate. An isolation region is arranged in the cut between the first fin and the second fin.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Jagar Singh, Hui Zang
  • Publication number: 20190131406
    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A body region is arranged partially in the substrate and partially in the first fin. A drain region is arranged partially in the substrate, partially in the first fin, and partially in the second fin. The body and drain regions respectively have opposite first and second conductivity types. A source region of the second conductivity type is located within the first well in the first fin, and a gate structure is arranged to overlap with a portion of the first fin. The first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate. An isolation region is arranged in the cut between the first fin and the second fin.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Jerome Ciavatti, Jagar Singh, Hui Zang
  • Publication number: 20190109197
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.
    Type: Application
    Filed: October 9, 2017
    Publication date: April 11, 2019
    Inventors: Haiting WANG, Wei ZHAO, Hui ZANG, Hong YU, Zhenyu HU, Scott BEASOR, Erik GEISS, Jerome CIAVATTI, Jae Gon LEE
  • Patent number: 10211206
    Abstract: Methods of connecting a read driver transistor to a PD and PU inverter of a two-port vertical SRAM via a shared GAA or a vertical cross-couple contact between a GAA of the read driver transistor and the bottom source/drain region of the PD and PU inverter and the resulting devices are provided. Embodiments include forming a first PD transistor, a first PU transistor, a second PU transistor, and a second PD transistor over a substrate; forming a first PG transistor and a second PG transistor over the substrate; forming a read transistor and a read driver transistor laterally separated in the first direction over the substrate, the read transistor and the read driver transistor adjacent to the second PG transistor and the first PD transistor, respectively; and connecting the read driver transistor, the first PD transistor, and the first PU transistor.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti
  • Publication number: 20190035791
    Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.
    Type: Application
    Filed: August 24, 2018
    Publication date: January 31, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti, Rinus Tek Po Lee
  • Publication number: 20180374857
    Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 27, 2018
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Hui ZANG, Jerome CIAVATTI
  • Patent number: 10163635
    Abstract: A method for preventing epitaxial merge between adjacent devices of a semiconductor is provided. Embodiments include forming a protection layer over a spacer formed over a first and second plurality of fins deposited within a substrate; pinching off a portion of the protection layer formed within a space between each of the plurality of fins; forming a planarization layer over the protection layer and the spacer; and etching a portion of the spacer to form inner sidewalls between each of the plurality of fins, outer sidewalls of a height greater than the height of the inner sidewalls for preventing the growth of the epitaxial layer beyond the outer sidewalls, or a combination thereof.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yi Qi, Hui Zang, Hsien-Ching Lo, Jerome Ciavatti, Judson Robert Holt
  • Patent number: 10164006
    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A first isolation region is arranged between the first fin and the second fin. A body region of a first conductivity type is arranged partially in the substrate and partially in the second fin. A drain region of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. A source region is arranged within the body region in the first fin. A gate structure is arranged to overlap with a portion of the first fin. A second isolation region is arranged within the first fin, and is spaced along the first fin from the first isolation region.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Jagar Singh, Hui Zang
  • Patent number: 10163915
    Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Jerome Ciavatti