Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.

Abstract: Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant.

Abstract: A method of encoding a first stream of digital signal data words is provided. A most recent value of the first stream of digital signal data words is received and memorized. A previous value of the first stream of digital data words is received and memorized. The most recent and the previous values of the stream of digital data words are combined to create a second data stream. The words are converted in the second data stream into a serial representation. The serial representation is transmitted on a single wire interface.

Abstract: A method of encoding a first stream of digital signal data words is provided. A most recent value of the first stream of digital signal data words is received and memorized. A previous value of the first stream of digital data words is received and memorized. The most recent and the previous values of the stream of digital data words are combined to create a second data stream. The words are converted in the second data stream into a serial representation. The serial representation is transmitted on a single wire interface.

Abstract: An operational amplifier (opamp) [74] coupled in a negative-feedback configuration [82] [84] comprising a driving opamp [76]; a linear controller [78]; and a mechanism [80] controlling the driving opamp's [76] offset. A voltage signal Vin provided by the feedback network [82][84] characterizes all errors caused by the driving opamp [76]. The controller [78] monitors this voltage and minimizes the signal-band spectral components thereof by inducing an offset in the driving opamp [76]. The offset control mechanism [80] has approximately constant gain and only little phase delay in the signal band.

Abstract: An analog-to-digital converter system [50D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal, d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, alpha, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero.

Abstract: A digital-to-analog converter system [150] based on a symmetrical circuit [152] comprising matched capacitors [104][106] for pseudo-passive, serial D/A conversion of a digital input signal x(n). Each bit x(n, k) of x(n) is converted by selecting one of the two capacitors in each capacitor pair [104][106] as the driving one, and charging it to plus/minus the reference voltage according to the value of x(n, k). The other capacitor in each capacitor pair [104][106] stores the previously generated voltage signal representing the bits of x(n) less significant than the bit x(n, k) being processed in the considered cycle k of the serial conversion process. After the driving capacitor has been charged according to x(n, k), the capacitors in each capacitor pair [104][106] are connected in parallel.

Abstract: An analog-to-digital converter system [50D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal, d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, alpha, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero.

Abstract: A technique to suppress idle tones in any mismatch-shaping encoder for use with a unit-element digital-to-analog converter. The arbitrary mismatch-shaping encoder provides a first set of signals which normally are intended to control directly the unit elements. A scrambler is used to interchange the first set of signals, thereby generating a second set of signals which are used to control the unit elements. The scrambler interchanges the signals as a function of a selector signal. A detecting circuit is used to evaluate in which clock cycles the unit elements have been used equally often. When this occurs, the selector signal is randomly assigned a new value in the following clock cycle.

Abstract: An operational amplifier (opamp) [74] coupled in a negative-feedback configuration [82][84] comprising a driving opamp [76]; a linear controller [78]; and a mechanism [80] controlling the driving opamp's [76] offset. A voltage signal Vin provided by the feedback network [82][84] characterizes all errors caused by the driving opamp [76]. The controller [78] monitors this voltage and minimizes the signal-band spectral components thereof by inducing an offset in the driving opamp [76]. The offset control mechanism [80] has approximately constant gain and only little phase delay in the signal band. The controller [78] may be a linear high-order Chebychev filter providing substantial gain in a wide frequency range, thereby efficiently suppressing all signal-band errors, including noise, harmonic distortion, and slew-rate errors, caused by the driving opamp [76].

Abstract: A delta-sigma modulator comprising a first quantizer providing a first digital signal d0(k) representing the input signal g(t); a loop filter with input signal paths; a loop quantizer providing a corrective digital signal d1(k) representing the loop filter's output signal y(t); an array of feedback DACs D/A converting the sum d(k)=df(k)=d0(k)+d1(k) of the first and the corrective digital signals and injecting feedback signals into the loop filter. The loop filter's input node is applied the difference of the input signal g(t) and the global analog feedback signal a3(t). The global feedback signal a3(t) is delayed several clock cycles with respect to the digital output signal d(k). The delay is used to carry out mismatch-shaping and deglitching algorithms in the feedback DACs. The feedback DACs' different delays and gain coefficients are designed such that the modulator is stable.

Abstract: A low-voltage constant-impedance analog switch based on a single MOSFET [328] as the main switching element. The constant-impedance on-state operation is obtained by connecting a charged capacitor [326] between the gate and source terminals of the MOSFET [328]. The switch can be compensated for the body effect, which may be necessary to obtain the required level of linearity. Low-voltage operation is made feasible by employing an internal feedback loop that locks in the switch's on-state. The switch can be implemented in a single-well CMOS bulk technology, and it can operate at supply-voltage differences that are only slightly higher than the technology's threshold voltage.

Abstract: A error-shaping digital-to-analog (D/A) converter system [100], consisting of a separator [102], a set of D/A converters [104] [108], a set of optional analog filters [106] [108], a summation device [112], and an optional analog filter [114]. The separator [102] separates the digital input signal into a set of low-resolution signals of which only one has significant power in the system's signal band. These signals are D/A converted by mismatch-shaping D/A converters [104] [108], in some embodiments filtered by analog filters [106] [108], and then added by the summing device [112]. Imperfections of the employed D/A converters [104] [108] will only cause very small errors in the signal band, such errors being essentially uncorrelated to the digital input signal. The D/A converter system is comparable to a scaled-element D/A converter in which the distortion is transformed into a noise component having very little power in the signal band.