Patents by Inventor Jhy-Jyi Sze

Jhy-Jyi Sze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7564083
    Abstract: An active pixel sensor is proposed by the invention. The position of the gate of the reset transistor is kept away from the interface of the isolation region and the silicon so that the depletion region does not reach the isolation. Accordingly, dark currents caused by isolation region damages can be avoided.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: July 21, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Jhy-Jyi Sze, Junbo Chen, Ming-Yi Wang
  • Publication number: 20090162971
    Abstract: A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed on the substrate. An opening is then formed to expose a surface of the doping area. A second poly-silicon layer is formed on the first poly-silicon layer and within the opening. The second poly-silicon layer is patterned to form a wire, while the first poly-silicon layer is patterned to form a gate. Finally, a source/drain is formed.
    Type: Application
    Filed: February 26, 2009
    Publication date: June 25, 2009
    Inventors: Jhy-Jyi Sze, Ming-Yi Wang, Junbo Chen
  • Patent number: 7547573
    Abstract: An image sensor and a method of manufacturing the same, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: June 16, 2009
    Assignees: United Microelectronics Corp., AltaSens Inc.
    Inventors: Tzeng-Fei Wen, Giuseppe Rossi, Ju-Hsin Yen, Chia-Huei Lin, Jhy-Jyi Sze, Chien-Yao Huang, Teng-Yuan Ko, Nien-Tsu Peng
  • Patent number: 7518171
    Abstract: A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed on the substrate. An opening is then formed to expose a surface of the doping area. A second poly-silicon layer is formed on the first poly-silicon layer and within the opening. The second poly-silicon layer is patterned to form a wire, while the first poly-silicon layer is patterned to form a gate. Finally, a source/drain is formed.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: April 14, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Jhy-Jyi Sze, Ming-Yi Wang, Junbo Chen
  • Publication number: 20080296705
    Abstract: A gate including a conductive buffer layer and a conductive layer is provided. The conductive buffer layer is disposed on a gate dielectric layer, and the average grain size of the conductive buffer layer is less than 100 nm. The conductive layer is disposed on the conductive buffer layer, and the average grain size of the conductive layer is greater than or equal to 100 nm. The disposition of the conductive buffer layer reduces the undesired effect caused by noise and dark current to the performance of the device.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 4, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Jhy-Jyi Sze
  • Publication number: 20080265354
    Abstract: An image sensor, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material.
    Type: Application
    Filed: June 27, 2008
    Publication date: October 30, 2008
    Inventors: Tzeng-Fei Wen, Giuseppe Rossi, Ju-Hsin Yen, Chia-Huei Lin, Jhy-Jyi Sze, Chien-Yao Huang, Teng-Yuan Ko, Nien-Tsu Peng
  • Publication number: 20080113477
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor including a substrate, a p type well, a light emitting diode, a p type gate structure and a plurality of n type gate structures is provided. The substrate has a photo sensitive region and a transistor device region, and the p type well is disposed in the substrate. The light emitting diode is disposed in the p type well and the substrate of the photo sensitive region. The p type gate structure is disposed on the substrate of the transistor device region. The n type gate structures are disposed on the substrate of the transistor device region.
    Type: Application
    Filed: December 11, 2007
    Publication date: May 15, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Jhy-Jyi Sze
  • Patent number: 7371599
    Abstract: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: May 13, 2008
    Assignee: United Microeletronics Corp.
    Inventor: Jhy-Jyi Sze
  • Publication number: 20080093633
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor including a substrate, a p type well, a light emitting diode, a p type gate structure and a plurality of n type gate structures is provided. The substrate has a photo sensitive region and a transistor device region, and the p type well is disposed in the substrate. The light emitting diode is disposed in the p type well and the substrate of the photo sensitive region. The p type gate structure is disposed on the substrate of the transistor device region. The n type gate structures are disposed on the substrate of the transistor device region.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 24, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Jhy-Jyi Sze
  • Publication number: 20080035968
    Abstract: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 14, 2008
    Inventor: Jhy-Jyi Sze
  • Publication number: 20080032438
    Abstract: An image sensor and a method of manufacturing the same, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 7, 2008
    Inventors: Tzeng-Fei Wen, Giuseppe Rossi, Ju-Hsin Yen, Chia-Huei Lin, Jhy-Jyi Sze, Chien-Yao Huang, Teng-Yuan Ko, Nien-Tsu Peng
  • Patent number: 7321141
    Abstract: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: January 22, 2008
    Assignee: United Microelectronics Corp.
    Inventor: Jhy-Jyi Sze
  • Publication number: 20070249077
    Abstract: A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed on the substrate. An opening is then formed to expose a surface of the doping area. A second poly-silicon layer is formed on the first poly-silicon layer and within the opening. The second poly-silicon layer is patterned to form a wire, while the first poly-silicon layer is patterned to form a gate. Finally, a source/drain is formed.
    Type: Application
    Filed: April 19, 2006
    Publication date: October 25, 2007
    Inventors: Jhy-Jyi Sze, Ming-Yi Wang, Junbo Chen
  • Publication number: 20070243676
    Abstract: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.
    Type: Application
    Filed: April 18, 2006
    Publication date: October 18, 2007
    Inventor: Jhy-Jyi Sze
  • Publication number: 20070241375
    Abstract: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.
    Type: Application
    Filed: April 17, 2006
    Publication date: October 18, 2007
    Inventor: Jhy-Jyi Sze
  • Publication number: 20060192261
    Abstract: An active pixel sensor is proposed by the invention. The position of the gate of the reset transistor is kept away from the interface of the isolation region and the silicon so that the depletion region does not reach the isolation. Accordingly, dark currents caused by isolation region damages can be avoided.
    Type: Application
    Filed: February 25, 2005
    Publication date: August 31, 2006
    Inventors: Jhy-Jyi Sze, Junbo Chen, Ming-Yi Wang
  • Patent number: 7008815
    Abstract: A method of manufacturing a self-aligned guard ring of a photo diode. The method includes defining a photo diode region on a semiconductor substrate and an isolation matter surrounding the photo diode region, forming a photo sensor in the photo diode region, covering a first mask on the photo sensor, forming a spacer around the first mask, covering a second mask on an edge of the isolation matter, and utilizing the first mask, the second mask, and the spacer to form a self-aligned guard ring surrounding the photo sensor.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: March 7, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Jhy-Jyi Sze, Ming-Yi Wang, Junbo Chen
  • Publication number: 20050158907
    Abstract: A method of fabricating an image sensor device is disclosed. In the method, a substrate having a plurality of trenches therein is provided. A first anti-reflective layer is formed on the surfaces of the trenches. An insulating layer is filled in the trenches for forming a plurality of shallow trench isolation regions. At least one photo sensitive region is formed within the substrate between neighboring shallow trench isolation regions. A second anti-reflective layer is formed at least covering the photo sensitive region. Because the first anti-reflective layer is formed on the surfaces of the trenches, and the second anti-reflective layer is formed on the photo sensitive region, the sensitivity of the image sensor device is improved.
    Type: Application
    Filed: July 15, 2004
    Publication date: July 21, 2005
    Inventors: Jhy-Jyi Sze, Min-Hua Tsai, Tzung-Han Tan, Hsin-Ping Wu, Chia-Huei Lin
  • Publication number: 20050158897
    Abstract: A method of fabricating an image sensor device is disclosed. In the method, a substrate having a plurality of trenches therein is provided. A first anti-reflective layer is formed on the surfaces of the trenches. An insulating layer is filled in the trenches for forming a plurality of shallow trench isolation regions. At least one photo sensitive region is formed within the substrate between neighboring shallow trench isolation regions. A second anti-reflective layer is formed at least covering the photo sensitive region. Because the first anti-reflective layer is formed on the surfaces of the trenches, and the second anti-reflective layer is formed on the photo sensitive region, the sensitivity of the image sensor device is improved.
    Type: Application
    Filed: January 21, 2004
    Publication date: July 21, 2005
    Inventors: Jhy-Jyi Sze, Min-Hua Tsai, Tzung-Han Tan, Hsin-Ping Wu, Chia-Huei Lin
  • Publication number: 20020181271
    Abstract: A dynamic random access memory cell, which does not need refresh cycle, comprises following elements: a transistor that gate is coupled to a word line, a capacitor that is coupled to source of the transistor, a switch that is coupled to the source, and a current source that is coupled to the source by the switch. Further, the current source is possible to be provided by a word line which is connected to gate of the transistor, and the switch is possible to be provided by bipolar junction transistor which is located between the capacitor and the current source.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 5, 2002
    Inventor: Jhy-Jyi Sze