Abstract: A sterile, packaged bioprosthetic heart valve includes an expandable support member, a bioprosthetic valve attached to the expandable support member, a layer of biocompatible material covering at least a portion of the expandable support member, and a microorganism-resistant container in which the bioprosthetic valve is sealed. The bioprosthetic valve includes a tissue component comprising glutaraldehyde-fixed bovine pericardium including interstices containing a dimensional stabilizer comprising an aqueous solution of propylene glycol.

Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.

Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

Abstract: A method is provided for implanting a valve having at least one valve leaflet within the cardiovascular system of a subject. One step of the method includes preparing a substantially dehydrated bioprosthetic valve and then providing an expandable support member having oppositely disposed first and second ends and a main body portion extending between the ends. Next, the substantially dehydrated bioprosthetic valve is attached to the expandable support member so that the substantially dehydrated bioprosthetic valve is operably secured within the main body portion of the expandable support member. The expandable support member is then crimped into a compressed configuration and placed at a desired location within the cardiovascular system of the subject. Either before or after placement at the desired location, fluid or blood re-hydrates the substantially dehydrated bioprosthetic valve.

Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.

Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.

Abstract: Described herein are imaging devices and associated methods. Devices and methods are described that include a plurality of topological phase modulators. In one example, the plurality of topological phase modulators includes an array of spiral vortices. Devices and methods are described that include a neural network to reconstruct images using data from the plurality of topological phase modulators.

Abstract: A semiconductor device includes a substrate, a channel layer, a source/drain region and a gate structure. The channel layer is located on the substrate, in which the channel layer includes silicon germanium. The source/drain region is adjacent to the channel layer. The gate structure is located on the channel layer, in which the gate structure includes a dielectric layer and a work function metal layer. The dielectric layer is located on the channel layer. The work function metal layer is located on the dielectric layer.

Abstract: A polarization-sensitive encoder, a polarimetric camera, and a method for polarimetric imaging in which the encoder includes a two-dimensional (2D) polycrystalline photonic-crystal film with nanofiber, multi-scale, self-assembled structures.

Abstract: A method for fabricating a radio-frequency (RF) device includes the steps of first providing a substrate comprising a core region and a non-core region, forming a shallow trench isolation (STI) in the substrate between the core region and the non-core region, forming a first gate oxide layer on the core region and the non-core region, forming a patterned mask on the non-core region and the STI, removing the first gate oxide layer on the core region, and then forming a second gate oxide layer on the core region.

Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

Abstract: This application relates to the field of lighting, and discloses an LED filament. The LED filament includes an LED chip unit, a light conversion layer, and an electrode. The light conversion layer covers the LED chip unit and part of the electrode, and a color of a light emitted by the LED filament after lighting is different from a color of the light conversion layer. This application has the characteristics of uniform light emission and good heat dissipation effect.

Abstract: Methods for reducing warpage and increasing the effectiveness of hybrid bond void testing are disclosed. A semiconductor package has a first side and a second side, with a dummy bond pad located on the second side, and at least one metal-containing layer between the first side and the second side (for example a redistribution layer). A warpage control structure is provided in the semiconductor package that extends from the first side into the semiconductor package, and is aligned with the dummy bond pad. The warpage control structure is made of a low-density filling. This relieves stress that causes/increases warpage. When a hybrid bond is formed between the semiconductor package and another semiconductor package, the warpage control structure maximizes acoustic wave penetration for testing the quality of the hybrid bond at the dummy bond pad.

Abstract: A deposition device includes a first chamber, a substrate support, a second chamber, a showerhead, a first reactant inlet, a second reactant, and a precursor inlet. The first chamber includes a diffusion zone and a reaction zone, and the diffusion zone is above the reaction zone. The substrate support is disposed in the reaction zone. The second chamber is disposed over the first chamber. The showerhead is disposed between the first chamber and the second chamber. The first reactant inlet communicates with the second chamber. The second reactant inlet communicates with the reaction zone of the first chamber. The precursor inlet communicates with the showerhead.

Abstract: A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

Abstract: An interconnect structure includes a barrier layer, an oxide glue layer, and an ultra low-k dielectric layer. The oxide glue layer is located on the barrier layer. The ultra low-k dielectric layer is located on the oxide glue layer, wherein the oxide glue layer is located between the barrier layer and the ultra low-k dielectric layer, and the ultra low-k dielectric layer has porosity less than 40%.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.

Abstract: A memory cell of a magnetic random access memory includes multiple layers disposed between a first metal layer and a second metal layer. At least one of the multiple layers include one selected from the group consisting of an iridium layer, a bilayer structure of an iridium layer and an iridium oxide layer, an iridium-titanium nitride layer, a bilayer structure of an iridium layer and a tantalum layer, and a binary alloy layer of iridium and tantalum.