Patents by Inventor Ji Feng

Ji Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685693
    Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ji-Feng Ying, Jhong-Sheng Wang, Baohua Niu
  • Patent number: 10672832
    Abstract: A magnetic detection circuit for a magnetic random access memory (MRAM) is provided. The magnetic detection circuit includes a sensing array including a plurality of sensing cells and a controller. Each of the sensing cells includes a first magnetic tunnel junction (MTJ) device. The controller is configured to access the first MRAM cells to detect the external magnetic field strength of the MRAM. The controller determines whether to stop the write operation of a plurality of memory cells of the MRAM according to the external magnetic field strength of the MRAM, and each of the memory cells includes a second MTJ device. The first MTJ device is smaller than the second MTJ device.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ji-Feng Ying, Baohua Niu
  • Publication number: 20200152701
    Abstract: A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Ji-Feng YING, Duen-Huei HOU
  • Publication number: 20200136018
    Abstract: A magnetic memory including a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 30, 2020
    Inventors: Ji-Feng YING, Jhong-Sheng WANG, Tsann LIN
  • Publication number: 20200098408
    Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
    Type: Application
    Filed: July 5, 2019
    Publication date: March 26, 2020
    Inventors: Tsann Lin, Ji-Feng Ying, Chih-Chung Lai
  • Publication number: 20200058340
    Abstract: A method of writing to a magnetic random access memory cell includes applying an alternating current signal to the magnetic random access memory cell having a first magnetic orientation, and applying a direct current pulse to the magnetic random access memory cell to change the magnetic orientation of the magnetic random access memory cell from the first magnetic orientation to a second magnetic orientation. The first magnetic orientation and the second magnetic orientation are different.
    Type: Application
    Filed: May 31, 2019
    Publication date: February 20, 2020
    Inventors: Ji-Feng YING, Jhong-Sheng WANG, Duen-Huei HOU
  • Patent number: 10541269
    Abstract: A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ji-Feng Ying, Duen-Huei Hou
  • Publication number: 20200020375
    Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.
    Type: Application
    Filed: April 5, 2019
    Publication date: January 16, 2020
    Inventors: Ji-Feng YING, Jhong-Sheng WANG, Baohua NIU
  • Publication number: 20200006425
    Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
    Type: Application
    Filed: April 2, 2019
    Publication date: January 2, 2020
    Inventors: Tsann Lin, Chien-Min Lee, Ji-Feng Ying
  • Publication number: 20190393265
    Abstract: A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Ji-Feng YING, Duen-Huei HOU
  • Publication number: 20190385690
    Abstract: A memory test system is disclosed that includes a memory integrated circuit (IC) and a memory functional tester. The memory IC includes a plurality of memory banks, where each memory bank includes a plurality of memory cells. The memory functional tester includes an adjustable voltage generator circuit, a read current measurement circuit, and a controller. The memory functional tester performs a write/read functional test on the memory bank over a number of write control voltages to determine a preferred write control voltage, where the preferred write control voltage is designated for use during subsequent write operations to the memory bank during an operational mode.
    Type: Application
    Filed: August 27, 2019
    Publication date: December 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Baohua NIU, Ji-Feng YING
  • Patent number: 10510410
    Abstract: In the disclosure, a non-volatile memory device includes a resistive memory cell and a write and read circuit. The write and read circuit is coupled to the resistive memory cell and configured to combine a perturbation AC signal with a first writing signal, so as to generate a second writing signal. Then, the write and read circuit applies the second writing signal to the resistive memory cell to program the resistive memory cell. The combination of the oscillation signal and the first writing signal (constant DC signal) and AC signal would penetrate the shielding effect of the insulating layer and free the stuck charges.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ji-Feng Ying, Baohua Niu, Jhong-Sheng Wang
  • Patent number: 10403385
    Abstract: A memory test system is disclosed that includes a memory integrated circuit (IC) and a memory functional tester. The memory IC includes a plurality of memory banks, where each memory bank includes a plurality of memory cells. The memory functional tester includes an adjustable voltage generator circuit, a read current measurement circuit, and a controller. The memory functional tester performs a write/read functional test on the memory bank over a number of write control voltages to determine a preferred write control voltage, where the preferred write control voltage is designated for use during subsequent write operations to the memory bank during an operational mode.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Baohua Niu, Ji-Feng Ying
  • Publication number: 20190248781
    Abstract: The present invention relates to novel thiazole-substituted indolin-2-ones as inhibitors of CSCPK and related kinases; to methods of inhibiting cancer stem cells by using a kinase inhibitor; to pharmaceutical compositions containing such compounds; and to methods of using such compounds in the treatment of a protein kinase related disorder in a mammal; and to processes of making such compounds and intermediates thereof.
    Type: Application
    Filed: November 14, 2018
    Publication date: August 15, 2019
    Inventors: Chiang Jia Li, Ji-Feng Liu, Youzhi Li, Wei Li, Harry Rogoff
  • Publication number: 20190241569
    Abstract: The invention provides novel inhibitors of cancer stem cells as well as cancer stem cell pathway kinase and other related kinases, pharmaceutical compositions and uses thereof in the treatment of cancer or a related disorder in a mammal, and methods of making such compounds and compositions.
    Type: Application
    Filed: November 30, 2018
    Publication date: August 8, 2019
    Inventors: Chiang Jia Li, Ji-Feng Liu, Wei Li, Amanda Gibeau, Harry Rogoff, Katsunori Tsuboi, Yosuke Takanashi, Shingo Tojo, Tomohiro Kodama, Katsumi Kubota, Toshio Kanai
  • Publication number: 20190237531
    Abstract: The present disclosure provides a display device and a manufacturing method thereof, and a display panel. The display panel may include a substrate defining a through hole; a driving wiring carried on the substrate; a solder pad being arranged on a back surface of the substrate. A first end of the driving wiring is located on a front surface of the substrate, and a second end of the driving wiring is connected to the solder pad via the through hole.
    Type: Application
    Filed: August 23, 2018
    Publication date: August 1, 2019
    Inventor: Ji-Feng Chen
  • Publication number: 20190223904
    Abstract: A pericardium puncture needle assembly includes a puncture needle and a guide wire capable of sliding in the puncture needle; or includes an outer sleeve and a guide wire capable of sliding in the outer sleeve; or includes an outer sleeve and a puncture needle and a guide wire capable of sliding in the outer sleeve, wherein after the puncture needle is pulled out of the outer sleeve, the guide wire is capable of sliding in the outer sleeve. The guide wire is made of a highly elastic material and includes a far-end bent segment. The far-end bent segment is formed by bending the guide wire and has a preset bending shape, and is suitable for being recovered from a stretching state to the preset bending shape. The tip of the far-end bent segment has a pointed structure.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Inventors: Ji FENG, Jie GONG, Xin HUA, Chang-sheng MA, Sophia Wang HANSEN
  • Patent number: 10332839
    Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is ?150 Mpa to ?500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: June 25, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Keen Zhang, Ji Feng, De-Jin Kong, Yun-Fei Li, Guo-Hai Zhang, Ching-Hwa Tey, Jing Feng
  • Publication number: 20190147950
    Abstract: In the disclosure, a non-volatile memory device includes a resistive memory cell and a write and read circuit. The write and read circuit is coupled to the resistive memory cell and configured to combine a perturbation AC signal with a first writing signal, so as to generate a second writing signal. Then, the write and read circuit applies the second writing signal to the resistive memory cell to program the resistive memory cell. The combination of the oscillation signal and the first writing signal (constant DC signal) and AC signal would penetrate the shielding effect of the insulating layer and free the stuck charges.
    Type: Application
    Filed: February 26, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ji-Feng Ying, Baohua Niu, Jhong-Sheng Wang
  • Publication number: 20190146045
    Abstract: An apparatus for measuring a magnetic field strength is provided. The apparatus includes a stage on which a sample to be measured is placed, a cantilever having a tip, an optical system having a light source and a light receiver, and a microwave power source. The tip is a diamond tip having a nitrogen vacancy defect. The optical system is configured such that excitation light from the light source is focused at the diamond tip. The cantilever is configured as a coaxial microwave antenna through which microwaves from the microwave power source are supplied to the diamond tip.
    Type: Application
    Filed: February 26, 2018
    Publication date: May 16, 2019
    Inventors: Baohua NIU, Ji-Feng YING