Patents by Inventor Ji Fu
Ji Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200098755Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.Type: ApplicationFiled: November 27, 2019Publication date: March 26, 2020Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
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Patent number: 10570507Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.Type: GrantFiled: April 10, 2018Date of Patent: February 25, 2020Assignee: United Microelectronics Corp.Inventors: Neng-Hsing Shen, Chien-Wen Yang, Chun-Man Li, Ji-Fu Kung, Ching-Pei Lin
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Patent number: 10548825Abstract: The present invention implements a strategy that combines an enzyme inhibition assay with a chemical dereplication process to identify active plant extracts and the particular compounds—diarylalkanes and/or diarylalkanols within those extracts that specifically inhibit binuclear enzyme function. Included in the present invention are compositions of matter comprised of one or more of diarylalkanes and/or diarylalkanols, which inhibit the activity of binuclear enzymes, particularly tyrosinase and which prevent melanin overproduction. The present invention also provides a method for inhibiting the activity of a binuclear enzyme, particularly tyrosinase and a method for preventing and treating diseases and conditions related to binuclear enzyme function. The present invention further includes a method for preventing and treating melanin overproduction and diseases and conditions of the skin related thereto.Type: GrantFiled: August 4, 2015Date of Patent: February 4, 2020Assignee: Unigen, Inc.Inventors: Qi Jia, Ji-Fu Zhao
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Patent number: 10529715Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.Type: GrantFiled: February 8, 2017Date of Patent: January 7, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
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Publication number: 20190276930Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.Type: ApplicationFiled: April 10, 2018Publication date: September 12, 2019Applicant: United Microelectronics Corp.Inventors: Neng-Hsing Shen, Chien-Wen Yang, Chun-Man Li, Ji-Fu Kung, Ching-Pei Lin
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Patent number: 10116435Abstract: A control circuit of a communication device includes: a periodic packet detection circuit, detecting a periodic packet of a data signal to generate a packet indication signal corresponding to the periodic packet; a frequency synthesis circuit, coupled to the periodic packet detection circuit, generating a working clock according to a reference clock; and a setting value generating circuit, coupled to the periodic packet detection circuit, generating a setting value according to a relationship between the frequencies of the working clock and the packet indication signal. The frequency synthesis circuit further adjusts the working clock according to the setting value to cause the frequency of the working clock to substantially be a predetermined multiple of the frequency of the packet indication signal.Type: GrantFiled: October 10, 2016Date of Patent: October 30, 2018Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Shih Jyun Yang, Ji-Fu Chang, Kuo-Kuang Lo
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Patent number: 10084424Abstract: A device and associated method for adjusting electrical impedance based on contact action are disclosed. The device includes a drive unit (1), a contact unit (2), a monitoring unit (3), and a control unit (4). The monitoring unit (3) measures an impedance signal of an electromagnetic functional material (7) in an alternating-current circuit, and transfers the impedance signal to the control unit (4). In response to the impedance signal measured by the monitoring unit (3), the control unit (4) controls the drive unit (1) to apply a mechanical load on the contact unit (2), which causes the contact unit (2) to contact the electromagnetic functional material (7). The value of a contact load is adjusted, so as to adjust the electrical impedance of the electromagnetic functional material (7), thereby achieving the objective of adjusting the impedance matching in the alternating-current circuit in real time.Type: GrantFiled: May 18, 2015Date of Patent: September 25, 2018Assignees: Peking University, Jilin UniversityInventors: Daining Fang, Hao Zhou, Yongmao Pei, Faxin Li, Hongwei Zhao, Ji Fu
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Publication number: 20180204838Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.Type: ApplicationFiled: February 8, 2017Publication date: July 19, 2018Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
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Patent number: 9958494Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.Type: GrantFiled: July 20, 2015Date of Patent: May 1, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Ming Hou, Ji-Fu Kung
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Publication number: 20180076787Abstract: A device and associated method for adjusting electrical impedance based on contact action are disclosed. The device includes a drive unit (1), a contact unit (2), a monitoring unit (3), and a control unit (4). The monitoring unit (3) measures an impedance signal of an electromagnetic functional material (7) in an alternating-current circuit, and transfers the impedance signal to the control unit (4). In response to the impedance signal measured by the monitoring unit (3), the control unit (4) controls the drive unit (1) to apply a mechanical load on the contact unit (2), which causes the contact unit (2) to contact the electromagnetic functional material (7). The value of a contact load is adjusted, so as to adjust the electrical impedance of the electromagnetic functional material (7), thereby achieving the objective of adjusting the impedance matching in the alternating-current circuit in real time.Type: ApplicationFiled: May 18, 2015Publication date: March 15, 2018Inventors: Daining Fang, Hao Zhou, Yongmao Pei, Faxin Li, Hongwei Zhao, Ji Fu
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Publication number: 20170310460Abstract: A control circuit of a communication device includes: a periodic packet detection circuit, detecting a periodic packet of a data signal to generate a packet indication signal corresponding to the periodic packet; a frequency synthesis circuit, coupled to the periodic packet detection circuit, generating a working clock according to a reference clock; and a setting value generating circuit, coupled to the periodic packet detection circuit, generating a setting value according to a relationship between the frequencies of the working clock and the packet indication signal. The frequency synthesis circuit further adjusts the working clock according to the setting value to cause the frequency of the working clock to substantially be a predetermined multiple of the frequency of the packet indication signal.Type: ApplicationFiled: October 10, 2016Publication date: October 26, 2017Inventors: Shih Jyun Yang, Ji-Fu Chang, Kuo-Kuang Lo
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Patent number: 9443970Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.Type: GrantFiled: October 28, 2015Date of Patent: September 13, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Hsin-Ming Hou, Yu-Cheng Tung, Ji-Fu Kung, Wai-Yi Lien, Ming-Tsung Chen
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Publication number: 20160193126Abstract: The present invention implements a strategy that combines an enzyme inhibition assay with a chemical dereplication process to identify active plant extracts and the particular compounds—diarylalkanes and/or diarylalkanols within those extracts that specifically inhibit binuclear enzyme function. Included in the present invention are compositions of matter comprised of one or more of diarylalkanes and/or diarylalkanols, which inhibit the activity of binuclear enzymes, particularly tyrosinase and which prevent melanin overproduction. The present invention also provides a method for inhibiting the activity of a binuclear enzyme, particularly tyrosinase and a method for preventing and treating diseases and conditions related to binuclear enzyme function. The present invention further includes a method for preventing and treating melanin overproduction and diseases and conditions of the skin related thereto.Type: ApplicationFiled: August 4, 2015Publication date: July 7, 2016Inventors: Qi Jia, Ji-Fu Zhao
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Patent number: 9299624Abstract: A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.Type: GrantFiled: January 21, 2014Date of Patent: March 29, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Ming Hou, Ji-Fu Kung
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Publication number: 20160049506Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.Type: ApplicationFiled: October 28, 2015Publication date: February 18, 2016Inventors: Hsin-Ming HOU, Yu-Cheng TUNG, Ji-Fu KUNG, Wai-Yi LIEN, Ming-Tsung CHEN
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Patent number: 9202914Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.Type: GrantFiled: March 14, 2012Date of Patent: December 1, 2015Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Hsin-Ming Hou, Yu-Cheng Tung, Ji-Fu Kung, Wai-Yi Lien, Ming-Tsung Chen
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Publication number: 20150323586Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Hsin-Ming Hou, Ji-Fu Kung
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Patent number: 9159809Abstract: A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other.Type: GrantFiled: February 29, 2012Date of Patent: October 13, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Ming Hou, Ji-Fu Kung
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Patent number: 9126913Abstract: The present invention implements a strategy that combines an enzyme inhibition assay with a chemical dereplication process to identify active plant extracts and the particular compounds—diarylalkanes and/or diarylalkanols within those extracts that specifically inhibit binuclear enzyme function. Included in the present invention are compositions of matter comprised of one or more of diarylalkanes and/or diarylalkanols, which inhibit the activity of binuclear enzymes, particularly tyrosinase and which prevent melanin overproduction. The present invention also provides a method for inhibiting the activity of a binuclear enzyme, particularly tyrosinase and a method for preventing and treating diseases and conditions related to binuclear enzyme function. The present invention further includes a method for preventing and treating melanin overproduction and diseases and conditions of the skin related thereto.Type: GrantFiled: March 13, 2014Date of Patent: September 8, 2015Assignee: Unigen, Inc.Inventors: Qi Jia, Ji-Fu Zhao
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Patent number: 9129076Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.Type: GrantFiled: December 8, 2013Date of Patent: September 8, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Ming Hou, Ji-Fu Kung