Abstract: A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.

Abstract: A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.

Abstract: A wafer fabrication outcome, such as wafer yield or wafer lifetime, is predicted by excluding uncontrollable but measurable internal/external noises of a DOE system, and by rendering relations between wafer design variables and wafer outcome outputs to be more causal, as well as the relations between variances for each of the wafer design variables and the wafer outcome outputs. With the aid of a wafer fabrication outcome predicting model formed by the more causal relations, precision of predicting wafer outcomes can be raised, and performance of wafer fabrication can be thus raised as a result.

Abstract: A layout correcting method and a layout correcting system are provided. The layout correcting method includes the following steps. An integrated circuit design layout is provided. A plurality of performance parameters of the integrated circuit design layout are analyzed. A plurality of devices under test is selected according to the performance parameters. A computer simulating process is performed on the devices under test and a direct probing process is performed on the devices under test. The direct probing process is an on-chip test for comparing each device under test and an environment condition thereof by a Boolean algebra algorithm. A plurality of differences between the results of the computer simulating process and the direct probing process is analyzed. The integrated circuit design layout is corrected according to differences between the results of the computer simulating process and the direct probing process.

Abstract: The present invention implements a strategy that combines an enzyme inhibition assay with a chemical dereplication process to identify active plant extracts and the particular compounds—diarylalkanes and/or diarylalkanols within those extracts that specifically inhibit binuclear enzyme function. Included in the present invention are compositions of matter comprised of one or more of diarylalkanes and/or diarylalkanols, which inhibit the activity of binuclear enzymes, particularly tyrosinase and which prevent melanin overproduction. The present invention also provides a method for inhibiting the activity of a binuclear enzyme, particularly tyrosinase and a method for preventing and treating diseases and conditions related to binuclear enzyme function. The present invention further includes a method for preventing and treating melanin overproduction and diseases and conditions of the skin related thereto.

Abstract: The identification and isolation of chromones and novel chromone compositions from plant sources that exhibit up-regulation of adiponectin production by adipocytes and the normalization of virtually hundreds of genes related to glucose and fatty acid metabolic and signaling pathways. The chromone compositions are effective in enhancing adiponectin production by adipocytes and regulating genes involved in fatty acid biosynthesis, mitochondrial ?-oxidation of fatty acids, steroid biosynthesis, gluconeogenesis, fat transport, PPAR?/RXR? liver signaling and xenobiotic metabolism. The chromone compositions can be used to increase insulin sensitivity, improve glucose tolerance, lower triglyceride levels and balance glucose levels in mammals. Included are methods for the prevention and treatment of a variety of diseases and conditions including, but not limited to insulin resistance, glucose intolerance, hyperglycemia, metabolic syndromes, dyslipidemia, and hypertriglyceridemia.

Abstract: The present invention implements a strategy that combines an enzyme inhibition assay with a chemical dereplication process to identify active plant extracts and the particular compounds—diarylalkanes and/or diarylalkanols within those extracts that specifically inhibit binuclear enzyme function. Included in the present invention are compositions of matter comprised of one or more of diarylalkanes and/or diarylalkanols, which inhibit the activity of binuclear enzymes, particularly tyrosinase and which prevent melanin overproduction. The present invention also provides a method for inhibiting the activity of a binuclear enzyme, particularly tyrosinase and a method for preventing and treating diseases and conditions related to binuclear enzyme function. The present invention further includes a method for preventing and treating melanin overproduction and diseases and conditions of the skin related thereto.

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract: A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal.

Abstract: Diarylalkanes having the following structure: wherein Ar1, Ar2, R6, R7 and n are as defined herein are provided. The disclosed compounds find utility as inhibitors of binuclear enzymes. Methods for inhibiting binuclear enzymes as well as methods and compositions for preventing and treating diseases and conditions associated with binuclear enzymes are also provided.

Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.

Abstract: A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other.

Abstract: A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.

Abstract: A wafer fabrication outcome, such as wafer yield or wafer lifetime, is predicted by excluding uncontrollable but measurable internal/external noises of a DOE system, and by rendering relations between wafer design variables and wafer outcome outputs to be more causal, as well as the relations between variances for each of the wafer design variables and the wafer outcome outputs. With the aid of a wafer fabrication outcome predicting model formed by the more causal relations, precision of predicting wafer outcomes can be raised, and performance of wafer fabrication can be thus raised as a result.

Abstract: An integrated circuit design and fabrication method includes the following steps. Firstly, an integrated circuit design layout is provided. Then, a first hotspot group and a second hotpot group are searched from the integrated circuit design layout. Then, a hotspot score is acquired according to the first hotspot group, the second hotpot group and a product functionality. If the hotspot score is higher than a criterion, the integrated circuit design layout is corrected according to the first hotspot group and the second hotpot group.

Abstract: A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal.

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield/lifetime domain, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract: Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections.

Abstract: The present invention implements a strategy that combines an enzyme inhibition assay with a chemical dereplication process to identify active plant extracts and the particular compounds—diarylalkanes and/or diarylalkanols within those extracts that specifically inhibit binuclear enzyme function. Included in the present invention are compositions of matter comprised of one or more of diarylalkanes and/or diarylalkanols, which inhibit the activity of binuclear enzymes, particularly tyrosinase and which prevent melanin overproduction. The present invention also provides a method for inhibiting the activity of a binuclear enzyme, particularly tyrosinase and a method for preventing and treating diseases and conditions related to binuclear enzyme function. The present invention further includes a method for preventing and treating melanin overproduction and diseases and conditions of the skin related thereto.

Abstract: The present invention implements a strategy that combines an enzyme inhibition assay with a chemical dereplication process to identify active plant extracts and the particular compounds—diarylalkanes and/or diarylalkanols within those extracts that specifically inhibit binuclear enzyme function. Included in the present invention are compositions of matter comprised of one or more of diarylalkanes and/or diarylalkanols, which inhibit the activity of binuclear enzymes, particularly tyrosinase and which prevent melanin overproduction. The present invention also provides a method for inhibiting the activity of a binuclear enzyme, particularly tyrosinase and a method for preventing and treating diseases and conditions related to binuclear enzyme function. The present invention further includes a method for preventing and treating melanin overproduction and diseases and conditions of the skin related thereto.