Abstract: A traffic categorization method and device are disclosed. A traffic categorization method according to one embodiment of the present invention may comprise the steps of: receiving flow data comprising information about a flow; scaling for the flow data; generating input data by removing, on the basis of a correlation, overlapping data from the scaled flow data; and categorizing a network traffic on the basis of the input data.

Abstract: A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.

Abstract: A power transistor having: a p-body region, coupled to a first voltage; a first p-type buried layer under the p-body region; a n-implant region surrounding the p-body region and the p-type buried layer; a p-implant region surrounding the n-implant region; and a p-implant guard ring region inserted into the n-implant region to split the n-implant region to a first part and a second part, wherein the first part of the n-implant region is between the p-body region and the p-implant guard ring region, and the second part of the n-implant region is between the p-implant guard ring region and the p-implant region; wherein the second part of the n-implant region has a Schottky contact region coupled to a second voltage via a metal contact.

Abstract: A manufacturing process of a DMOS device in a drift region in a semiconductor substrate, having: forming a polysilicon layer above the drift region; forming a block layer above the polysilicon layer; etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the drift region; implanting dopants through the window to the drift region to form a body region; forming blocking spacers to wrap side walls of the polysilicon layer; implanting dopants into the body region under a window shaped by the blocking spacers to form a body pickup region; etching away the blocking spacers; performing a masking step to form gates; forming ONO spacers to wrap side walls of the gates; and performing a masking step to form source regions and drain pickup regions.

Abstract: An LDMOS device with sinker link. The LDMOS device has a buried layer, a first well region and a sinker linking the buried layer and the first well region. The LDMOS device has a trench with its upper portion surrounded by the first well region and its lower portion surrounded by the sinker. The trench is formed so that the sinker can be formed by ion implantation through the trench. The trench is filled with non-conductive material.

Abstract: The present disclosure discloses a lateral transistor having a source region, a drain region, a gate near the source region side and a field dielectric positioned in or atop a portion of a well region between the drain region and the gate. The lateral transistor further includes a non-conductive field plate positioning layer positioned atop a portion of the field dielectric and separated laterally from the gate with a first lateral distance, a lateral conductive field plate positioned atop the non-conductive field plate positioning layer and separated laterally from the gate with a second lateral distance and a vertical trenched field plate contact extending vertically from a top surface of an interlayer dielectric layer through the interlayer dielectric layer to reach and contact with the lateral conductive field plate.

Abstract: A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.

Abstract: A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask.

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P? type first epitaxial layer formed on the buried layer, a P? type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

Abstract: A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask.

Abstract: A method for fabricating a semiconductor device including: forming a block layer above a well region of a first doping type in a semiconductor substrate, wherein the block layer has an opening for defining a first region in an upper part of the well region and has sidewalls at sides of the opening; implanting dopants of a second doping type into the well region through the opening of the block layer to form the first region; implanting dopants of the first doping type into the first region in the manner of large-angle-tilt dopants implantation to form a second region for a first transistor, and to form a third region for a second transistor; and forming, for both of the first transistor and the second transistor, a fourth region between the second region and the third region.

Abstract: A method for fabricating a LDMOS device in a well region of a semiconductor substrate, including: etching a polysilicon layer above the well region through a window for a body region; and forming spacers at side walls of the polysilicon layer, to define positions of source regions in the well region.

Abstract: A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask.

Abstract: A method for fabricating a LDMOS device in a well region of a semiconductor substrate, including: forming a body region and a source layer in the well region through a window of a polysilicon layer above the well region, wherein the body region has a deeper junction depth than the source layer; forming spacers at side walls of the polysilicon layer; and etching through the source layer through a window shaped by the spacers, wherein the source layer under the spacers is protected from etching, and is defined as source regions of the LDMOS device.

Abstract: A lateral DMOS device with peak electric field moved below a top surface of the device along a body-drain junction is introduced. The LDMOS has a deep body and a drift region formed by a series of P-type and N-type implants, respectively. The implant doses and depths are tuned so that the highest concentration gradient of the body-drift junction is formed below the surface, which suppresses the injection and trapping of hot holes in the device drain-gate oxide region vicinity, and the associated device performance changes, during operation in breakdown.

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P? type first epitaxial layer formed on the buried layer, a P? type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

Abstract: A high voltage DMOS device using conventional silicon BCD (Bipolar CMOS DMOS) technology has a P-type buried layer and an N-type buried layer, a first epitaxial layer and a second epitaxial layer. The high voltage DMOS device is characterized in high breakdown voltage, good robustness and low Ron through controlling the thickness of the epitaxial layers, the dose and forming energy of the buried layers. In addition, the high voltage DMOS may further has a shallow drain region to further improve robustness.

Abstract: A Schottky diode comprising a cathode region, an anode region and a guard ring region, wherein the anode region may comprise a metal Schottky contact, and the guard ring region may comprise an outer guard ring and a plurality of inner open stripes inside the outer guard ring, and wherein the inner open stripes has a shallower junction depth than the outer guard ring.

Abstract: A method for fabricating a LDMOS device in a semiconductor substrate of a first doping type, including: implanting a series of dopants into the semiconductor substrate using a first mask, and forming a first region of a second doping type adjacent to the surface of the semiconductor substrate, a second region of the first doping type located beneath the first region, and a third region of the second doping type located beneath the second region; implanting dopants into the semiconductor substrate using a second mask, and forming a fourth region of the second doping type adjacent to the first, second and third regions, wherein the fourth region extends from the surface of the semiconductor substrate to approximately the same depth as the third region; and implanting dopants into the first region using a third mask, and form a first well of the first doping type.

Abstract: A Schottky diode comprising a cathode region, an anode region and a guard ring region, wherein the anode region may comprise a metal Schottky contact, and the guard ring region may comprise an outer guard ring and a plurality of inner open stripes inside the outer guard ring, and wherein the inner open stripes has a shallower junction depth than the outer guard ring.