Abstract: A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region touches the body region. By designing the device such that the enhanced drift region overlaps and compensates the lateral tail of the body region of the LDMOS transistor, the Ron*area product is reduced. Accordingly, the on-resistance is significantly reduced while minimally affecting the breakdown voltage of the device.

Abstract: A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another, and separating the drain regions from the source regions. The method includes providing a semiconductor material, growing a first insulating layer on top of the semiconductor material, depositing a polysilicon layer on top of the first insulating layer, defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another, and forming a plurality of drain regions and a plurality of source regions in the semiconductor material in alternating rows or columns. The plurality of chains separates the plurality of drain regions from the plurality of source regions.

Abstract: A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another, and separating the drain regions from the source regions. The method includes providing a semiconductor material, growing a first insulating layer on top of the semiconductor material, depositing a polysilicon layer on top of the first insulating layer, defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another, and forming a plurality of drain regions and a plurality of source regions in the semiconductor material in alternating rows or columns. The plurality of chains separates the plurality of drain regions from the plurality of source regions.

Abstract: A zener zap device is formed in a fabrication process using a tungsten plug process having standard sized contact openings. The zener zap device includes first and second regions of opposite conductivity types formed in a semiconductor layer. A dielectric layer overlaying the surface of the semiconductor layer includes first and second contact openings positioned above and exposing a portion of the first and second regions respectively. The first contact opening is an enlarged contact opening having dimensions larger than the standard sized contact opening. A first metal contact formed in the first enlarged contact opening includes tungsten sidewall and aluminum formed in electrical contact with the exposed surface of the first region. In one embodiment, the second contact opening is also an enlarged contact opening for forming a second metal contact having tungsten sidewall and aluminum in electrical contact with the exposed surface of the second region.

Abstract: A method for fabricating a bipolar transistor includes forming a first region of a first conductivity type in a semiconductor structure to form a collector region and forming a second region of a second conductivity type in the first region to form a base region. A first mask is applied including an opening defining an emitter region of the bipolar transistor. The method further includes a triple implantation process using the first mask. Thus, a third region of the first conductivity type is formed in the first region and overlaid the second region. A fourth region of the second conductivity type is formed in the second region and is more heavily doped than the second region. A fifth region of the first conductivity type is formed in the second region and above the fourth region. The fifth region forms the emitter region of the bipolar transistor.

Abstract: A method for fabricating a bipolar transistor includes forming a first region of a first conductivity type in a semiconductor structure to form a collector region and forming a second region of a second conductivity type in the first region to form a base region. A first mask is applied including an opening defining an emitter region of the bipolar transistor. The method further includes a triple implantation process using the first mask. Thus, a third region of the first conductivity type is formed in the first region and overlaid the second region. A fourth region of the second conductivity type is formed in the second region and is more heavily doped than the second region. A fifth region of the first conductivity type is formed in the second region and above the fourth region. The fifth region forms the emitter region of the bipolar transistor.

Abstract: A method for fabricating complementary metal-oxide-semiconductor (CMOS) devices and circuits resulting therefrom are provided. The method includes forming the source and drain regions of the CMOS device by out-diffusion of ions injected into a conductive spacer. The method also includes forming the gate electrode after the source and drain regions have been activated by heat treatment. By forming the gate electrode after heat treating the source and drain regions, the material used to form the gate electrode is not distorted due to heat.

Abstract: A CMOS device is disclosed in which p-channel and n-channel MOS transistors are formed on the same substrate. Each of the MOS transistors has a gate insulating layer formed on the substrate; a gate having a gate body and a spacer formed on both sidewalls of the gate body; a drain region of a first conductivity type formed in the substrate and beneath the gate body; a channel region of a second conductivity type formed at both sides of the first heavily doped impurity region and beneath the spacer; and a source region of the first conductivity type formed in the substrate and between the channel region and the device isolating region. With this CMOS device, the channel length can be controlled to about 0.1 mm and less and hot-carrier effect can be minimized.

Abstract: Methods of forming MOS transistors include the steps of forming hot-carrier suppression electrodes on opposing sides of an insulatedgate of a field effect transistor, to reduce hot-carrier degradation parasitics and reduce gate-to-drain overlap capacitance (C.sub.gd). These methods include the steps of forming at least a first hot-carrier suppression electrode between a drain electrode and an insulated gate electrode of a field effect transistor. The hot-carrier suppression electrode reduces the likelihood of hot-carrier degradation parasitics by inhibiting hot electron injection into the gate oxide of the field effect transistor and also reduces the gate-to-drain region capacitance by eliminating the need to establish a fully-overlapped geometry between the transistor's gate and lightly doped drain (LDD) region extension as a way to prevent parasitic injection. According to a preferred embodiment of the present invention, a first electrically insulating layer (e.g., SiO.sub.