Abstract: A motor-driving apparatus for driving a motor having a plurality of windings respectively corresponding to a plurality of phases is provided. The motor-driving apparatus includes a first inverter having a plurality of first switching devices and connected to first ends of the plurality of windings and a second inverter having a plurality of second switching devices and connected to second ends of the plurality of windings. A third switching device is configured to selectively connect and disconnect points at which a number of turns of each of the windings is divided in a preset ratio. A controller is configured to adjust an on/off state of the first to third switching devices based on required output of the motor.

Abstract: A battery module includes a sub module including a cell stack having a plurality of battery cells and a pair of bus bar frames respectively coupled to one side and the other side of the cell stack; a module housing configured to accommodate the sub module and configured to have an air inlet and an air outlet formed to circulate air; a sprinkler provided through the module housing at one side of the cell stack in a stacking direction; and an outlet closing device configured to move by a buoyancy generated by a cooling water introduced into the module housing through the sprinkler so that the air outlet is closed.

Abstract: A pixel includes an organic light emitting diode (OLED), a pixel circuit, and first and second transistors. The OLD includes a cathode electrode connected to a second power source. The pixel circuit includes a driving transistor having a gate electrode initialized by a third power source. The driving transistor controls the amount of current flowing from a first power source to the second power source via the OLED. The first transistor is connected between a fourth power source and the second power source and an anode electrode of the OLED. The first transistor is turned on based on a scan signal is supplied to a scan line. The second transistor is connected between a data line and the pixel circuit. The second transistor is turned on when the scan signal is supplied to the ith scan line.

Abstract: Provided are methods for autonomous vehicle yielding, which can include obtaining sensor data associated with an environment and obtaining a rule indicative of a target expressive operation. Some methods described also include determining whether the sensor data meets a first criterion, applying the rule in response to the sensor data meeting the first criterion, evaluating a first trajectory of the autonomous vehicle, and selecting a second trajectory. Systems and computer program products are also provided.

Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.

Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.

Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

Abstract: A method of fabricating a memory device may include forming a first conductive line extending over a substrate in a first direction, forming a memory cell pillar on the first conductive line, and forming a second conductive line extending over the memory cell pillar in a second direction that intersects the first direction, such that the first and second conductive lines vertically overlap with the memory cell pillar interposed between the first and second conductive lines. The memory cell pillar may include a heating electrode layer and a resistive memory layer. The resistive memory layer may include a wedge memory portion and a body memory portion. The wedge memory portion may contact the heating electrode layer and may have a width that that changes with increasing distance from the heating electrode layer. The body memory portion may be connected to the wedge memory portion.

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.

Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

Abstract: Disclosed is to provide a composition derived from a natural material and which has an excellent effect of enhancing cognitive function and a method for preparing the same. The extract and composition according to one aspect of the present disclosure are derived from a natural material and thus are safe. It can prevent, ameliorate and treat cognitive decline. Therefore, it allows to improve the quality of life of the elderly population without concerns about side effects and promote development of the related industry.

Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.