Patents by Inventor Ji-Hyun Jeong
Ji-Hyun Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10714686Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines.Type: GrantFiled: January 12, 2018Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sungwon Kim, Sung-Ho Eun, Ilmok Park, Junghoon Park, Seulji Song, Ji-Hyun Jeong
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Patent number: 10685682Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.Type: GrantFiled: October 23, 2018Date of Patent: June 16, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hyun Jeong, Jae-hyun Park
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Publication number: 20200152869Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: JI-HYUN JEONG, JIN-WOO LEE, GWAN-HYEOB KOH, DAE-HWAN KANG
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Patent number: 10644069Abstract: A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.Type: GrantFiled: September 19, 2018Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hyun Jeong, Dae-Hwan Kang, Du-Eung Kim, Kwang-Jin Lee
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Publication number: 20200136037Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.Type: ApplicationFiled: December 24, 2019Publication date: April 30, 2020Inventors: Ji-Hyun JEONG, Ilmok PARK, Si-Ho SONG
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Patent number: 10636843Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: GrantFiled: February 21, 2019Date of Patent: April 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Patent number: 10566386Abstract: A method of manufacturing a variable memory device includes forming a switching layer on a first conductive layer, forming a heating layer on the switching layer, the heating layer extending in a first direction, performing a first patterning process on the first conductive layer, the switching layer, and the heating layer to form a first trench extending in a second direction intersecting the first direction, forming variable resistance patterns on the heating layer, forming a second conductive layer on the variable resistance patterns, and performing a second patterning process on the switching layer, the heating layer, and the second conductive layer to form a second trench extending in the first direction and being between the variable resistance patterns.Type: GrantFiled: May 29, 2018Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ji-Hyun Jeong
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Patent number: 10566529Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: GrantFiled: January 5, 2018Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
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Patent number: 10547000Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.Type: GrantFiled: June 21, 2018Date of Patent: January 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hyun Jeong, Ilmok Park, Si-Ho Song
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Publication number: 20190341547Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Seul-ji Song, Sung-won Kim, Il-mok Park, Jong-chul Park, Ji-hyun Jeong
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Patent number: 10403817Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.Type: GrantFiled: January 11, 2018Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Seul-ji Song, Sung-won Kim, Il-mok Park, Jong-chul Park, Ji-Hyun Jeong
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Publication number: 20190189692Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: ApplicationFiled: February 21, 2019Publication date: June 20, 2019Inventors: Ji-hyun JEONG, Gwan-hyeob KOH, Dae-hwan KANG
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Publication number: 20190172502Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.Type: ApplicationFiled: October 23, 2018Publication date: June 6, 2019Inventors: Ji-hyun Jeong, Jae-hyun Park
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Publication number: 20190140022Abstract: A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.Type: ApplicationFiled: September 19, 2018Publication date: May 9, 2019Inventors: JI-HYUN JEONG, Dae-Hwan Kang, Du-Eung Kim, Kwang-Jin Lee
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Publication number: 20190123272Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.Type: ApplicationFiled: June 21, 2018Publication date: April 25, 2019Inventors: Ji-Hyun JEONG, ILMOK PARK, Si-Ho SONG
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Publication number: 20190123277Abstract: A method of manufacturing a variable memory device includes forming a switching layer on a first conductive layer, forming a heating layer on the switching layer, the heating layer extending in a first direction, performing a first patterning process on the first conductive layer, the switching layer, and the heating layer to form a first trench extending in a second direction intersecting the first direction, forming variable resistance patterns on the heating layer, forming a second conductive layer on the variable resistance patterns, and performing a second patterning process on the switching layer, the heating layer, and the second conductive layer to form a second trench extending in the first direction and being between the variable resistance patterns.Type: ApplicationFiled: May 29, 2018Publication date: April 25, 2019Inventor: Ji-Hyun JEONG
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Patent number: 10263040Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: GrantFiled: February 27, 2018Date of Patent: April 16, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Publication number: 20190091275Abstract: Disclosed is to provide a composition derived from a natural material and which has an excellent effect of enhancing cognitive function and a method for preparing the same. The extract and composition according to one aspect of the present disclosure are derived from a natural material and thus are safe. It can prevent, ameliorate and treat cognitive decline. Therefore, it allows to improve the quality of life of the elderly population without concerns about side effects and promote development of the related industry.Type: ApplicationFiled: August 23, 2018Publication date: March 28, 2019Inventors: Hyungsu KIM, Ayoung KIM, Juewon KIM, Si Young CHO, Yong-Deog HONG, Seung Soo CHUNG, Suk Jin KO, Ji Hyun JEONG, Ji Woong AHN
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Publication number: 20190019950Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures.Type: ApplicationFiled: January 12, 2018Publication date: January 17, 2019Inventors: Sungwon Kim, Sung-Ho Eun, Ilmok Park, Junghoon Park, Seulji Song, Ji-Hyun Jeong
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Publication number: 20180375023Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.Type: ApplicationFiled: January 11, 2018Publication date: December 27, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Seul-ji SONG, Sung-won KIM, II-mok PARK, Jong-chul PARK, Ji-hyun JEONG