Patents by Inventor Ji-Hyun Jeong
Ji-Hyun Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10056431Abstract: A variable resistance memory device may include a word line extending in a first direction, a bit line extending in a second direction crossing the first direction, a phase-changeable pattern provided between the word line and the bit line, a bottom electrode provided between the phase-changeable pattern and the word line, and a spacer provided on a side surface of the bottom electrode and between the phase-changeable pattern and the word line. The bottom electrode may include a first portion and a second portion, and the second portion is provided between the first portion and the spacer. The first and second portions of the bottom electrodes may have different lengths from each other in the second direction.Type: GrantFiled: September 10, 2017Date of Patent: August 21, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ilmok Park, Sungwon Kim, Seulji Song, Ji-Hyun Jeong
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Publication number: 20180190718Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Publication number: 20180158872Abstract: A variable resistance memory device may include a word line extending in a first direction, a bit line extending in a second direction crossing the first direction, a phase-changeable pattern provided between the word line and the bit line, a bottom electrode provided between the phase-changeable pattern and the word line, and a spacer provided on a side surface of the bottom electrode and between the phase-changeable pattern and the word line. The bottom electrode may include a first portion and a second portion, and the second portion is provided between the first portion and the spacer. The first and second portions of the bottom electrodes may have different lengths from each other in the second direction.Type: ApplicationFiled: September 10, 2017Publication date: June 7, 2018Inventors: ILMOK PARK, Sungwon KIM, Seulji SONG, Ji-Hyun JEONG
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Publication number: 20180145252Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: ApplicationFiled: January 5, 2018Publication date: May 24, 2018Inventors: JI-HYUN JEONG, JIN-WOO LEE, GWAN-HYEOB KOH, DAE-HWAN KANG
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Patent number: 9941333Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: GrantFiled: October 7, 2016Date of Patent: April 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Patent number: 9887354Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: GrantFiled: October 18, 2016Date of Patent: February 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
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Publication number: 20170244031Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: ApplicationFiled: October 18, 2016Publication date: August 24, 2017Inventors: JI-HYUN Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
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Publication number: 20170243923Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: ApplicationFiled: October 7, 2016Publication date: August 24, 2017Inventors: Ji-hyun JEONG, Gwan-hyeob KOH, Dae-hwan KANG
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Patent number: 8748884Abstract: A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed.Type: GrantFiled: April 6, 2011Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hyun Jeong, JaeHee Oh, Heung Jin Joo, Sung-Ho Eun
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Patent number: 8724411Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.Type: GrantFiled: October 3, 2011Date of Patent: May 13, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Young Kim, Ki Whan Song, Jae Hee Oh, Ji-Hyun Jeong
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Patent number: 8518790Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.Type: GrantFiled: December 3, 2012Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-in Kim, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
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Publication number: 20130143382Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.Type: ApplicationFiled: December 3, 2012Publication date: June 6, 2013Applicant: Samsung Electronics Co., LtdInventors: Jung-in KIM, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
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Patent number: 8324067Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.Type: GrantFiled: March 1, 2010Date of Patent: December 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-in Kim, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
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Publication number: 20120092946Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.Type: ApplicationFiled: October 3, 2011Publication date: April 19, 2012Inventors: Jin-Young KIM, Ki Whan SONG, Jae Hee OH, Ji-Hyun JEONG
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Patent number: 8119503Abstract: Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.Type: GrantFiled: July 7, 2009Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kong-Soo Lee, Kyoung-Seok Kim, Sang-Jin Park, Chang-Hoon Lee, Ji-Hyun Jeong, Jae-Hyun Park, Jae-Hee Oh
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Publication number: 20110248235Abstract: A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed.Type: ApplicationFiled: April 6, 2011Publication date: October 13, 2011Inventors: Ji-Hyun Jeong, JaeHee Oh, Heung Jin Joo, Sung-Ho Eun
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Patent number: 8030129Abstract: A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.Type: GrantFiled: December 21, 2009Date of Patent: October 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hyun Jeong, Jae-Hee Oh, Jae-Hyun Park
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Patent number: 8021966Abstract: A method of fabricating a nonvolatile memory device includes; forming a first sacrificial layer pattern including a first open area that extends in a first direction on a lower dielectric layer, forming a pre-lower dielectric layer pattern including a recess that extends in the first direction using the first sacrificial layer pattern, forming a second sacrificial layer pattern including a second open area that extends in a second direction on the pre-lower dielectric layer pattern and the first sacrificial layer pattern, wherein the second open area intersects the first open area, forming a lower dielectric layer pattern including contact holes spaced apart in the recess using the first sacrificial layer pattern and second sacrificial layer pattern, wherein the contact holes extend to a bottom of the lower dielectric layer pattern, and forming a bottom electrode in the contact hole.Type: GrantFiled: December 22, 2009Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hyun Jeong, Jae-Hee Oh, Jae-Hyun Park
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Publication number: 20100227449Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.Type: ApplicationFiled: March 1, 2010Publication date: September 9, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-in KIM, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
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Publication number: 20100181549Abstract: A PRAM device may include an insulating interlayer, a diode, a metal silicide layer, a barrier spacer, an outer spacer, a lower electrode, a phase-changeable layer and an upper electrode. The insulating interlayer may be formed on a substrate. The insulating interlayer may have a contact hole. The diode may be formed in the contact hole. The metal silicide layer may be formed on the diode. The barrier spacer may be formed on an upper surface of the metal silicide layer and a side surface of the contact hole. The outer spacer may be formed on the barrier spacer. The lower electrode may be formed on the barrier spacer. The phase-changeable layer may be formed on the lower electrode. The upper electrode may be formed on the phase-changeable layer.Type: ApplicationFiled: January 14, 2010Publication date: July 22, 2010Inventors: Song-Yi Kim, Heung-Jin Joo, Dae-Hwan Kang, Ji-Hyun Jeong, Jun-Hyok Kong