Patents by Inventor Ji Man HONG

Ji Man HONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210096774
    Abstract: A data storage device may include a storage and a controller. The storage includes a plurality of memory cells. The controller is configured to map a logical address of a host on a first physical address of the storage to perform data exchanges with respect to the storage. The controller includes an address error management component. The address error management component is configured to generate a first checker based on the first physical address. The address error management component transmits the first checker and the first physical address to the storage. When an address error occurs in the first physical address based on an address error check information that is transmitted from the storage, the address error management component is configured to remap the logical address on a second physical address.
    Type: Application
    Filed: May 8, 2020
    Publication date: April 1, 2021
    Applicant: SK hynix Inc.
    Inventors: Gi Bbeum HAN, Kyung Bum KIM, Ji Man HONG, Na Ra SHIN
  • Publication number: 20200367774
    Abstract: The present invention is provided with a noninvasive intracranial pressure measuring device for measuring an intracranial pressure of a person, includes goggles worn on the face of the person; a first probe provided on the goggles, and emitting ultrasonic waves to an optic nerve sheath so as to measure a diameter of the optic nerve sheath; a second probe provided on the goggles, and emitting ultrasonic waves to the ophthalmic artery so as to measure a pulsatility index of the ophthalmic artery; and a controller for calculating the intracranial pressure on the basis of measured values received from the first probe and the second probe.
    Type: Application
    Filed: December 24, 2018
    Publication date: November 26, 2020
    Applicant: AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventor: Ji Man HONG
  • Patent number: 10839925
    Abstract: Provided herein may be a method of operating a semiconductor memory device. The method of operating a semiconductor memory device may include programming selected memory cells with first page data, and programming the selected memory cells with second page data and programming a flag cell with flag data according to a foggy-fine programming scheme. The flag data may indicate whether data programmed according to the program operation is the first page data or the second page data. An operation of programming the flag cell with the flag data may be initiated after foggy programming of the second page data is completed.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Publication number: 20200282254
    Abstract: A muscle-strengthening passive and active motion device includes: a joint supporter supporting a body part that is bendable or stretchable with a joint region; a driver driving the joint supporter by being combined to the joint supporter; and a controller controlling the driver, wherein the controller is capable of accelerating or decelerating a driving speed of the joint supporter.
    Type: Application
    Filed: December 29, 2016
    Publication date: September 10, 2020
    Applicant: AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventor: Ji Man HONG
  • Patent number: 10755785
    Abstract: A memory system may include performing a first read operation on first data stored in first memory cells coupled to a first word line, performing an error correction operation on the first data, performing an interference program operation on second memory cells coupled to a second word line when the error correction operation fails, and performing a second read operation on the first data stored in the first memory cells after performing the interference program operation.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10685714
    Abstract: Provided herein may be a memory device and a memory system including the memory device. The memory device may include a memory block including a plurality of memory cells, a peripheral circuit configured to perform a selective erase operation on the memory cells, and control logic configured to control, during the selective erase operation, the peripheral circuit to apply an erase allowable voltage to a selected word line among a plurality of word lines in the memory block, apply an erase voltage to a selected string among a plurality of strings in the memory block, and float unselected word lines and unselected strings.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: June 16, 2020
    Assignee: SK hynix Inc.
    Inventors: Ji Man Hong, Tae Hoon Kim
  • Patent number: 10658049
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10658051
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10658050
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Publication number: 20200111533
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Applicant: SK hynix Inc.
    Inventor: Ji Man HONG
  • Publication number: 20200111532
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventor: Ji Man HONG
  • Publication number: 20200111531
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventor: Ji Man HONG
  • Patent number: 10610239
    Abstract: A non-invasive cerebral perfusion increasing device including four cuffing pad units and a control unit which is connected to the cuffing pad units and is equipped with a blood pressure sensing module and a compression control module. In the non-invasive cerebral perfusion increasing device each cuffing pad unit respectively includes a compression pad, a compression control member and a blood pressure sensing member. The blood pressure sensing module uses the blood pressure sensing members to sense the systolic blood pressure values of the portions of each of the limbs where they are attached and the compression control module controls the degree of compression of each compression pad by controlling the compression control member to a setting desired by the user based on the sensed blood pressure value, such that the blood flow applied to the limbs is blocked and, indirectly, cerebral perfusion is increased.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: April 7, 2020
    Assignee: AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventor: Ji Man Hong
  • Patent number: 10580503
    Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10564896
    Abstract: A data storage device includes a nonvolatile memory device configured to include a plurality of pages; and a controller configured to control an operation of the nonvolatile memory device, wherein the controller stores first data in a first least significant bit (LSB) page, stores the first data in a first most significant bit (MSB) page which is coupled to the same first word line as the first LSB page, when a first condition is satisfied, and stores second data in the first MSB page after the first data is stored in the first MSB page.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10541036
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10460809
    Abstract: An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell includes accessing a plural-level cell memory block in an N-bit cell mode, determining a degree of disturbance of the plural-level cell memory block, designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination, and accessing the M-bit group in an M-bit cell mode.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: October 29, 2019
    Assignee: SK hynix Inc.
    Inventor: Ji-Man Hong
  • Publication number: 20190295662
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Application
    Filed: November 13, 2018
    Publication date: September 26, 2019
    Inventor: Ji Man HONG
  • Publication number: 20190287625
    Abstract: Provided herein may be a memory device and a memory system including the memory device. The memory device may include a memory block including a plurality of memory cells, a peripheral circuit configured to perform a selective erase operation on the memory cells, and control logic configured to control, during the selective erase operation, the peripheral circuit to apply an erase allowable voltage to a selected word line among a plurality of word lines in the memory block, apply an erase voltage to a selected string among a plurality of strings in the memory block, and float unselected word lines and unselected strings.
    Type: Application
    Filed: October 23, 2018
    Publication date: September 19, 2019
    Inventors: Ji Man HONG, Tae Hoon KIM
  • Publication number: 20190267091
    Abstract: An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell includes accessing a plural-level cell memory block in an N-bit cell mode, determining a degree of disturbance of the plural-level cell memory block, designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination, and accessing the M-bit group in an M-bit cell mode.
    Type: Application
    Filed: September 17, 2018
    Publication date: August 29, 2019
    Inventor: Ji-Man HONG