Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.

Abstract: An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell includes accessing a plural-level cell memory block in an N-bit cell mode, determining a degree of disturbance of the plural-level cell memory block, designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination, and accessing the M-bit group in an M-bit cell mode.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.

Abstract: Provided herein may be a memory device and a memory system including the memory device. The memory device may include a memory block including a plurality of memory cells, a peripheral circuit configured to perform a selective erase operation on the memory cells, and control logic configured to control, during the selective erase operation, the peripheral circuit to apply an erase allowable voltage to a selected word line among a plurality of word lines in the memory block, apply an erase voltage to a selected string among a plurality of strings in the memory block, and float unselected word lines and unselected strings.

Abstract: An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell includes accessing a plural-level cell memory block in an N-bit cell mode, determining a degree of disturbance of the plural-level cell memory block, designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination, and accessing the M-bit group in an M-bit cell mode.

Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.

Abstract: A memory system may include performing a first read operation on first data stored in first memory cells coupled to a first word line, performing an error correction operation on the first data, performing an interference program operation on second memory cells coupled to a second word line when the error correction operation fails, and performing a second read operation on the first data stored in the first memory cells after performing the interference program operation.

Abstract: Provided is an elastic band for correcting a joint deformity and enhancing a joint function, the elastic band including: a first band to be attached to an outer part of a joint of a finger or toe and to the back of a hand or the top of a foot, and having a strip shape; a second band to be attached to an inner part of a last joint of the finger or toe while surrounding the inner part, and having a width increasing towards an end to surround side parts of the finger or toe together; and a connecting portion disposed between the first band and the second band to integrally connect the first band and the second band, and having a width gradually decreasing and then increasing from the first band towards the second band, and a mounting device of the elastic band.

Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.

Abstract: Provided herein may be a method of operating a semiconductor memory device. The method of operating a semiconductor memory device may include programming selected memory cells with first page data, and programming the selected memory cells with second page data and programming a flag cell with flag data according to a foggy-fine programming scheme. The flag data may indicate whether data programmed according to the program operation is the first page data or the second page data. An operation of programming the flag cell with the flag data may be initiated after foggy programming of the second page data is completed.

Abstract: A data storage device includes a nonvolatile memory device configured to include a plurality of pages; and a controller configured to control an operation of the nonvolatile memory device, wherein the controller stores first data in a first least significant bit (LSB) page, stores the first data in a first most significant bit (MSB) page which is coupled to the same first word line as the first LSB page, when a first condition is satisfied, and stores second data in the first MSB page after the first data is stored in the first MSB page.

Abstract: A data storage device includes a nonvolatile memory device including a first page group coupled to a first word line and a second page group coupled to a second word line, which is subsequent to the first word line in order of a write operation; and a controller suitable for, after an abnormal power-off during a write operation to the first page group, copying a first data stored in a weak page of the first page group to a stable page of the second page group when a first error correction operation to data stored in the first page group is a success.

Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.

Abstract: A functional glove for holding an ultrasonic probe includes: a body for encompassing the thumb and at least a part of the back of the hand of an inspector operating the ultrasonic probe; a probe fixing part coupled to the body so as to encompass and fix the fingers of the inspector and the ultrasonic probe; and a wrist protection part connected to the body so as to encompass and protect the wrist of the inspector.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The method of operating a semiconductor memory device may include performing a program operation on a Least Significant Bit (LSB) of a page, and performing a program operation on a flag cell and a Most Significant Bit (MSB) of the page based on an operation of verifying at least one of a plurality of program states. The data stored in the flag cell may be data indicating whether data programmed according to the program operation is LSB data or MSB data.

Abstract: A method for operating a data storage device including a plurality of pages includes performing a read operation to a first page of the nonvolatile memory device according to a read voltage; adjusting the read voltage based on a number of error bits in the read-out data according to the read voltage; performing the read operation to the first page according to the adjusted read voltage; and performing a re-program operation to the first page based on a number of on cells as a result of the read operation according to the adjusted read voltage.

Abstract: A data storage device includes a nonvolatile memory device including a first page group coupled to a first word line and a second page group coupled to a second word line, which is subsequent to the first word line in order of a write operation; and a controller suitable for, after an abnormal power-off during a write operation to the first page group, copying a first data stored in a weak page of the first page group to a stable page of the second page group when a first error correction operation to data stored in the first page group is a success.

Abstract: The present invention relates to a composition comprising erythropoietin (EPO) as an active ingredient for aiding surgical procedures for treating ischemic vascular diseases. The present invention also relates to a method for treating ischemic vascular diseases using a combination of the composition and the invasive procedure for sufficient disruption of the physical barriers for new neovascularization. The composition for aiding surgical or invasive procedures according to the present invention would be beneficial for the success rate and safety issue of a variety of surgical procedures such as minimally invasive operations performed on a patient suffering from a variety of cerebral ischemic vascular diseases including ischemic stroke and moyamoya disease, and can be widely used in the treatment of a variety of ischemic vasculopathies in cardiac or peripheral artery system.

Abstract: A nonvolatile memory device includes a memory block including a plurality of memory cells which are coupled to a plurality of word lines; and a control unit configured to perform a read operation in response to a read command for target memory cells which are coupled to a target word line, wherein the control unit performs the read operation by applying a read bias voltage to the target word line, applying a first pass bias to a monitoring word line, applying a second pass bias to one or more adjacent word lines adjacent to the target word line, and applying a third pass bias to remaining word lines.

Abstract: A data storage device may include: a nonvolatile memory device comprising a plurality of memory blocks, each having a plurality of pages, wherein each of the pages is divided into a plurality of segments having predetermined segment offset values, and the plurality of segments are grouped into a plurality of segment groups, each comprising segments having the same segment offset value; and a controller suitable for storing data in a first segment group among the plurality of segment groups until the first segment group includes no more empty segments.