Abstract: A method for decoding multiword information comprises steps (a) to (h). In step (a), a multiword information cluster including high protective words and low protective words is provided, wherein the multiword information, high protective words and low protective words can be ECC data, BIS data and LDC data, respectively. In step (b), the low protective words are partitioned into multiple groups. In step(c), the low protective words are de-interleaved, so as to generate a low protective word cluster including multiple segments corresponding to the multiple groups. In step (d), any error of the low protective words is detected, so as to generate segment erasure indicators with localities. In step (e), the low protective words and the segment erasure indicators are stored into a first memory, e.g., a DRAM. In step (f), the segment erasure indicators are stored into a second memory, e.g., a SRAM. In step (g), erasure bits of the low protective word are generated based on the segment erasure indicators.

Abstract: A method for decoding multiword information comprises multiple steps. In step (a), a multiword information cluster, e.g., ECC, including high protective codewords, e.g., BIS, and low protective codewords, e.g., LDC, is provided. In step (b), the high and low protective codewords are stored into a first memory, e.g., DRAM. In step (c), the high protective codewords are decoded to generate high protective word erasure indicators showing whether decoding errors occur. In step (d), the high protective word erasure indicators are stored into a second memory, e.g., SRAM. In step (e), the low protective codewords are decoded. In the meanwhile, an erasure bit for a low protective codeword is marked by finding high protective codewords close to the low protective codeword in the multiword information cluster and looking up the high protective word erasure indicators of the high protective codewords close to the low protective codeword.

Abstract: A method for decoding an error correction code (ECC) block includes: providing a plurality of flags, wherein each flag is utilized to label at least one codeword of the ECC block as an error-free codeword; and detecting whether a flag corresponding to a specific codeword is asserted, and skipping calculating a syndrome of the specific codeword if the flag is asserted.

Abstract: The present invention provides a method and system for converting an input code into an output code. The method includes: determining a plurality of input code subsets of the input code; converting the input code subsets into a plurality of output code subsets, respectively; and merging the output code subsets to generate the output code. The system includes a splitter, for determining a plurality of input code subsets of the input code; a mapper, coupled to the splitter, for converting the input code subsets into a plurality of output code subsets, respectively; and a merger, coupled to the mapper, for merging the output code subsets to generate the output code.

Abstract: A data buffering method used when performing a read operation on an optical storage medium is disclosed. After a first data unit having an unidentifiable and temporarily undeducible ID address is reproduced through the read operation, the method starts storing the first data unit and subsequently reproduced data units into a buffer memory in turn. After a second ID address of a second data unit of the subsequently reproduced data units is identified, the method deduces a target memory address of the buffer memory according to the second ID address and a target ID address. A buffer start pointer is then set according to the deduced target memory address.

Abstract: Disclosed is a method for converting an input code into an output code. The method includes: determining a plurality of input code subsets of the input code; converting the input code subsets into a plurality of output code subsets, respectively; and merging the output code subsets to generate the output code.

Abstract: An optical disc drive includes a pickup head, a DSP coupled to the pickup head, a buffer memory, a decoder coupled to the DSP and the buffer memory, and a control unit coupled to the decoder. The pickup head reads data stored in a blu-ray disc to generate an electrical signal. The DSP receives the electrical signal from the pickup head, and generates an LDC block and a BIS block according to the electrical signal. The decoder receives the LDC block and the BIS block from the DSP, generates user data and control data according to the LDC block and the BIS block respectively, and stores the user data and the control data into the buffer memory. The control unit controls the operation of the decoder.

Abstract: A GPS receiver device comprises a receiver, an oscillator, a memory unit, a temperature sensor, and a processor. The oscillator generates frequency with drift errors occurring at a variety of different temperatures. The memory unit stores coefficients of a plurality of polynomial equations. Each polynomial equation fits a temperature range versus corresponding drift errors. The temperature sensor detects ambient temperature of the receiver. The processor determines which temperature range the ambient temperature belongs to, reads the coefficients of the corresponding polynomial equation from the memory unit according to the determined temperature range, and calculates the drift error of the oscillator at the ambient temperature.

Abstract: A key bit position of a first Gray code is determined based on the bit values of the first Gray code. The first Gray code and a second Gray code that differs from the first Gray code only in the key bit position correspond to two associated numbers that differ by one.

Abstract: An integrated apparatus for multi-standard optical media includes a compact disc/digital versatile disc (CD/DVD) processor, a high-definition DVD (HDDVD) processor and a Blu-ray disc (BD) processor; a memory unit connected to the CD/DVD processor, the HDDVD processor and the BD processor to provide a storage resource; and a shared error correction code (ECC) engine for encoding or decoding the CD/DVD data stream, the HDDVD data stream and the BD data stream. Therein, the ECC engine further has a syndrome/parity generator to encode the data stream or to obtain the syndrome information from the data stream; and an erasure generator to obtain the possible error position information from the data stream. Thereby, the complexity and cost of the integrated apparatus can be reduced.

Abstract: A method for decoding multiword information comprises steps (a) to (h). In step (a), a multiword information cluster including high protective words and low protective words is provided, wherein the multiword information, high protective words and low protective words can be ECC data, BIS data and LDC data, respectively. In step (b), the low protective words are partitioned into multiple groups. In step(c), the low protective words are de-interleaved, so as to generate a low protective word cluster including multiple segments corresponding to the multiple groups. In step (d), any error of the low protective words is detected, so as to generate segment erasure indicators with localities. In step (e), the low protective words and the segment erasure indicators are stored into a first memory, e.g., a DRAM. In step (f), the segment erasure indicators are stored into a second memory, e.g., a SRAM. In step (g), erasure bits of the low protective word are generated based on the segment erasure indicators.

Abstract: A key bit position of a first Gray code is determined based on the bit values of the first Gray code. The first Gray code and a second Gray code that differs from the first Gray code only in the key bit position correspond to two associated numbers that differ by one.

Abstract: A method for decoding multiword information comprises multiple steps. In step (a), a multiword information cluster, e.g., ECC, including high protective codewords, e.g., BIS, and low protective codewords, e.g., LDC, is provided. In step (b), the high and low protective codewords are stored into a first memory, e.g., DRAM. In step (c), the high protective codewords are decoded to generate high protective word erasure indicators showing whether decoding errors occur. In step (d), the high protective word erasure indicators are stored into a second memory, e.g., SRAM. In step (e), the low protective codewords are decoded. In the meanwhile, an erasure bit for a low protective codeword is marked by finding high protective codewords close to the low protective codeword in the multiword information cluster and looking up the high protective word erasure indicators of the high protective codewords close to the low protective codeword.

Abstract: A method for computing parity characters for a codeword of a cyclic code successively generates a sum of an output value and a respective message character of a first message section adjacent to parity characters within a first block. The method then successively multiplies a respective sum by corresponding coefficients of a generator polynomial to generate at least one product. The method further successively multiplies a respective message character of every message section other than the first message section by coefficients of a corresponding shift polynomial to generate a plurality of products, before finally, successively summing corresponding products to generate the output value.

Abstract: The present invention provides a decoding system and method for an optical disk storage device to receive and decode the data of the disk. The present invention does not need to increase the clock frequency and the bus width of the decoding system, it can effectively decrease the access times to the data buffer and the system response time by changing the structure of the conventional decoding system, in this way the present invention increases the parallel processing capability and the decoding speed of the system, thus, it can enhance the entire device to become a high speed optical storage device.

Abstract: The invention is a method of calculating a key equation polynomial. The key equation comprises an errata locator polynomial and an errata evaluator polynomial. The errata locator polynomial decomposes to a plurality of coefficients. Some or all of the plurality of coefficients are formed by adding up decomposed data. The method comprises a coefficient calculation procedure for the errata locator polynomial of updating at least two coefficients, or two decomposed data of the coefficient calculation procedure, or a combination of the above in a single clock cycle simultaneously to get the errata locator polynomial.

Abstract: An automated generation method of hardware/software interface for SIP development is provided. The method comprises establishing a template wherein an interface template is established for enabling a user to quickly generate a system architecture, designing a hardware access program wherein a driver is provided for a model of the interface template so that a user is able to run the driver to verify the correctness of a designed IP, designing a driver for creating a driver complying with a driver of an OS, and repeatedly verifying a created design module and a management module so as to determine the correctness of codes created by an interface module.

Abstract: The present invention provides an error correction method that is used in full response read channels. This method includes the steps of: obtaining a read signal from a storage medium and converting the read signal into channel bits that are recorded in the storage medium, such as a DVD disk, in the NRZI format; and using the Viterbi detector to determine whether bit state transitions in the channel bits occur within a predetermined run-lengths of the RLL codes. If transitions occur within the predetermined run-lengths, then the values of the bits with state transitions are corrected.

Abstract: An encoding/decoding system in an optical disk storage device for performing compact disc/digital video disk (CD/DVD) encoding/decoding of data. The encoding/decoding system includes address mappers for C1, C2, CD P/Q, and DVD inner/outer codes respectively and a shareable Reel-Solomon (RS) encoder/decoder. The shareable RS encoder/decoder is capable of selectively being coupled to either one of the address mappers. When the encoding/decoding system is encoding, the shareable RS encoder/decoder employs a generation polynomial of RS code to generate a parity code of 2T symbols and output a codeword of N symbols, wherein the values of N and 2T are associated with the selected address mapper.

Abstract: A Viterbi detector for use in a partial response maximum likelihood (PRML) signal processing apparatus. The Viterbi detector can be used for different partial response (PR) equalizations with different parameters, and can be used for different PRML signal processing apparatuses such as high speed optical disk systems. The Viterbi detector includes an input buffer, a branch metric calculation unit, an add-compare-select circuit, a path memory unit, and a clock buffer. The Viterbi is designed based on a union trellis diagram relation obtained by combining trellis diagram relations associated with the PR equalizations with the parameters. According to the invention, the Viterbi detector has advantages of saving hardware space and conveniently changing PR equalizations with different parameters.