Patents by Inventor Jia-Rong Wu
Jia-Rong Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9312121Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.Type: GrantFiled: October 9, 2014Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yi-Hui Lee, Tsung-Hung Chang, Ching-Wen Hung, Jia-Rong Wu, Ching-Ling Lin, Chih-Sen Huang, Yi-Wei Chen, Chia-Chang Hsu, Shu-Min Huang, Hsin-Fu Huang
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Patent number: 9306032Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.Type: GrantFiled: October 25, 2013Date of Patent: April 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Chih-Sen Huang, Po-Chao Tsao, Ching-Wen Hung, Jia-Rong Wu, Chien-Ting Lin
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Publication number: 20160064327Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.Type: ApplicationFiled: September 24, 2014Publication date: March 3, 2016Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
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Patent number: 9263392Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.Type: GrantFiled: October 30, 2014Date of Patent: February 16, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
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Publication number: 20160013104Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.Type: ApplicationFiled: August 10, 2014Publication date: January 14, 2016Inventors: Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Ching-Ling Lin, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen, Chun-Hsien Lin
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Patent number: 9230816Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the gate structure and the ILD layer; forming a patterned hard mask on the dielectric layer; forming an opening in the dielectric layer and the ILD layer; performing a silicide process for forming a silicide layer in the opening; removing the patterned hard mask and un-reacted metal after the silicide process; and forming a contact plug in the opening.Type: GrantFiled: February 24, 2015Date of Patent: January 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Jia-Rong Wu, Chih-Sen Huang, Yi-Wei Chen, Chia Chang Hsu
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Publication number: 20150243663Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a dual silicide approach of the embodiment, a substrate having a first area with plural first metal gates and a second area with plural second metal gates is provided, wherein the adjacent first metal gates and the adjacent second metal gates are separated by an insulation. A dielectric layer is formed on the first and second metal gates and the insulation. The dielectric layer and the insulation at the first area are patterned by a first mask to form a plurality of first openings. Then, a first silicide is formed at the first openings. The dielectric layer and the insulation at the second area are patterned by a second mask to form a plurality of second openings. Then, a second silicide is formed at the second openings.Type: ApplicationFiled: February 24, 2014Publication date: August 27, 2015Applicant: United Microelectronics Corp.Inventors: Ching-Wen Hung, Chih-Sen Huang, Jia-Rong Wu, Ching-Ling Lin
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Patent number: 9117886Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.Type: GrantFiled: November 27, 2013Date of Patent: August 25, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Chih-Sen Huang, Jia-Rong Wu, Ching-Wen Hung
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Publication number: 20150145027Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Chih-Sen Huang, Jia-Rong Wu, Ching-Wen Hung
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Publication number: 20150118836Abstract: A method of fabricating a semiconductor device is disclosed. Provided is a substrate having a dummy gate formed thereon, a spacer on a sidewall of the dummy gate and a first dielectric layer surrounding the spacer. The dummy gate is removed to form a gate trench. A gate dielectric layer and at least one work function layer is formed in the gate trench. The work function layer and the gate dielectric layer are pulled down, and a portion of the spacer is laterally removed at the same time to widen a top portion of the gate trench. A low-resistivity metal layer is formed in a bottom portion of the gate trench. A hard mask layer is formed in the widened top portion of the gate trench.Type: ApplicationFiled: October 28, 2013Publication date: April 30, 2015Applicant: United Microelectronics Corp.Inventors: Ching-Ling Lin, Chih-Sen Huang, Jia-Rong Wu, Ching-Wen Hung, Po-Chao Tsao
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Publication number: 20150118835Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.Type: ApplicationFiled: October 25, 2013Publication date: April 30, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Chih-Sen Huang, Po-Chao Tsao, Ching-Wen Hung, Jia-Rong Wu, Chien-Ting Lin
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Patent number: 9006110Abstract: A method for fabricating a patterned structure of a semiconductor device includes: forming first mandrels and second mandrels on a substrate, wherein a first spacing is defined between the two adjacent first mandrels and a second spacing is defined between the two adjacent second mandrels, the first spacing being wider than the second spacing; forming a cover layer to cover the first mandrels while exposing the second mandrels; etching the cover layer and the second mandrels; removing the cover layer; concurrently forming first spacers on the sides of the first mandrels and a second spacers on the sides of the second mandrels after removing the cover layer; and transferring a layout of the first and second spacers to the substrate so as to form fin-shaped structures.Type: GrantFiled: November 8, 2013Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Chien-Ying Sun, En-Chiuan Liou, Jia-Rong Wu, Ching-Wen Hung
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Publication number: 20150097248Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.Type: ApplicationFiled: November 21, 2014Publication date: April 9, 2015Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
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Patent number: 8962490Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon, wherein at least one metal gate is formed in the ILD layer and at least one source/drain region is adjacent to two sides of the metal gate; forming a first dielectric layer on the ILD layer; forming a second dielectric layer on the first dielectric layer; performing a first etching process to partially remove the second dielectric layer; utilizing a first cleaning agent for performing a first wet clean process; performing a second etching process to partially remove the first dielectric layer; and utilizing a second cleaning agent for performing a second wet clean process, wherein the first cleaning agent is different from the second cleaning agent.Type: GrantFiled: October 8, 2013Date of Patent: February 24, 2015Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Jia-Rong Wu, Chih-Sen Huang, Chieh-Te Chen
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Publication number: 20150011734Abstract: An isolated protein having SEQ ID NO:1 and an isolated gene encoding the protein are provided. The protein is related with basal thermotolerance of plants having the protein.Type: ApplicationFiled: December 1, 2013Publication date: January 8, 2015Applicant: National Central UniversityInventors: Shaw-Jye Wu, Lian-Chin Wang, Jia-Rong Wu
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Patent number: 8928112Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.Type: GrantFiled: July 21, 2014Date of Patent: January 6, 2015Assignee: United Microelectronics Corp.Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
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Patent number: 8912074Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.Type: GrantFiled: July 13, 2014Date of Patent: December 16, 2014Assignee: United Microelectronics Corp.Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
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Publication number: 20140332920Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. Apart of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.Type: ApplicationFiled: July 21, 2014Publication date: November 13, 2014Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
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Publication number: 20140322891Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.Type: ApplicationFiled: July 13, 2014Publication date: October 30, 2014Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
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Patent number: 8823132Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.Type: GrantFiled: January 8, 2013Date of Patent: September 2, 2014Assignee: United Microelectronics Corp.Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu