Abstract: A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test input signals to a plurality of embedded memory blocks, receives data output signals output by the memory blocks in response to the test input signals, and verifies the data output signal based on the test input signals. The routing boxes are placed to form a common bus between the test controller and the memory blocks to transmit the signals between the test controller and the memory blocks.

Abstract: A method for displaying images on multiple monitors with different refresh rates is disclosed. To prevent screen tearing, the surface containing image data is not released when the access by the master monitor is completed until the slave monitor or monitors finish access. To synchronize images with a predefined playback speed, the surface containing a new image received from the application is not flipped onto the screens until receiving a predefined synchronization indicator.

Abstract: A method for displaying images on multiple monitors with different refresh rates is disclosed. To prevent screen tearing, the surface containing image data is not released when the access by the master monitor is completed until the slave monitor or monitors finish access. To synchronize images with a predefined playback speed, the surface containing a new image received from the application is not flipped onto the screens until receiving a predefined synchronization indicator.

Abstract: An insect capturing apparatus includes a Stirling engine to facilitate the generation of a gaseous flow for introducing insects within a receptacle. The Stirling engine acts with an external heat source that may produce insect-attractive chemical emissions as by-products of heat generation. The insect-attractant emissions may be utilized to attract insects to the apparatus for capture within the receptacle.

Abstract: A digital controlled oscillator (DCO) of a digital phase lock loop (PLL) is disclosed, wherein a fractional DCO structure is employed to provide the required target clock for comparing with the generated output clock. Comparison results of phase differences then enable a K-counter loop filter for changing its stored value. A control logic circuit is enabled to control a tapped-delay line for adjusting the currently output 'clock to coincide the requirement of the target clock when the stored value increases/decreases to K/−K. Additionally, signals from all-digital counter filter can be input to the fractional DCO structure to calibrate the frequency of the target clock according to environment without additional circuits.

Abstract: A data processing apparatus consists of an input buffer for storing one or more pieces of line data which each are formed of pieces of picture data and adding a specific code to each of the line data, a searching section for searching the input buffer for one or more specific codes, a search control section for (1) calculating a number Dx of pieces of picture data stored in the input buffer, (2) instructing the searching section to search the input buffer for one or more specific codes when the number Dx reaches a reference number, (3) repeatedly adding an incremental value to the reference number to increase the reference number in cases where no specific code is found out by the searching section, and (4) repeatedly instructing the searching section to search the input buffer for one or more specific codes when the number Dx reaches the reference number increased until at least one specific code is found out by the searching section, a data taking out section for taking out one or more pieces of line data s