Abstract: A digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said two or more obtained values to obtain a value, y, using a factorized polynomial interpolation.

Abstract: The present invention provides an active substrate and a display device for realizing color display of an electronic paper. The active substrate comprises a first substrate and a pixel electrode layer formed on the first substrate, and further comprises a color filter layer formed on the pixel electrode layer and a protective layer formed on the color filter layer, wherein the color filter layer comprises: a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit that are sequentially arranged; wherein the materials of the red sub-pixel unit, the green sub-pixel unit and the blue sub-pixel unit are quantum dot materials that emit red light, green light and blue light respectively when excited by the ambient light. The display device according to the present invention comprises an electrophoretic display device and an electrowetting display device.

Abstract: The invention relates to a current collector. The current collector include a metal foil and a graphene film covered on at least one surface of the metal foil. The invention also relates to an electrode of an electrochemical battery and the electrochemical battery using the current collector.

Abstract: The present invention provides a kind of high voltage direct current broadband domain corona current measurement system, including the sampling resistance sensor, the UHV local end measurement unit, the optical fiber transmission unit, the safe location measurement unit and the upper monitor; The sampling resistance sensor samples the corona current signal of the HVDC line, and converts the corona current signal to the voltage signal, the UHV local end measurement unit collects the voltage signal, and obtains the optical signal by photoelectric conversion, the optical signal transforms to the safe location measurement unit by the optical fiber transmission unit, the safe location measurement unit converts the optical signal to the voltage signal, the host computer performs processing, storing and displaying with the voltage signal.

Abstract: The present invention discloses an array substrate, comprising a substrate and common signal lines arranged on the substrate. The common signal lines comprise a first common signal line and a second common signal line which are spaced from each other; a first active layer is arranged between the first common signal line and the second common signal to form a first switch transistor; and the second common signal line is connected to a common electrode arranged above the second common signal line. A gate and a second active layer are sequentially arranged above the first active layer; a source signal line and a drain signal line are arranged on the second active layer to form a second switch transistor, and the drain signal line is connected to a pixel electrode arranged above the drain signal line.

Abstract: The present invention provides an array substrate and a manufacturing method thereof and a display device, belonging to the field of display technology and solving the problems that the display quality is reduced and the normal watching is affected due to alignment shifting during alignment in an existing thin film transistor liquid crystal display. The array substrate of the present invention includes a plurality of sub-pixel units, wherein a plurality of light forming units corresponding to the sub-pixel units are arranged on a light-exiting surface of the array substrate, and each of the light forming unit is configured to form light of a color of the sub-pixel units corresponding thereto. When the array substrate of the present invention is applied to the display device, the display quality of the display device may be improved.

Abstract: A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xK function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.

Abstract: A silver nanowire thin film comprising a silver nanowire layer formed over a base substrate and a protective layer formed over the silver nanowire layer. A method for manufacturing the silver nanowire thin film comprising: forming a silver nanowire layer over a base substrate; forming a protective layer over the silver nanowire layer; forming a pattern of the silver nanowire layer covered with the protective layer thereon through a patterning process. An array substrate and a display device are further provided.

Abstract: The present invention provides a mask, on which a preset pattern is provided. First test patterns for determining an amount of a position offset of the mask during its movement are provided on the mask at a first side of the preset pattern and a second side of the preset pattern opposite to the first side, respectively. When being moved in a direction from the first side to the second side by a standard distance, the mask can determine whether a position offset occurs to the mask during its movement, and determine an amount of the position offset if a position offset occurs. Thus, the position offset of the mask can be corrected, thereby obtaining an accurate predetermined pattern on a glass substrate.

Abstract: Embodiments of the invention disclose an array substrate and a method for manufacturing the same, and a display device. The method for manufacturing an array substrate comprising: forming a gate metal layer, wherein the gate metal layer comprises gate lines; film-forming an active layer and film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after film-forming the active layer and before film-forming the signal line metal layer, the method further comprising: hollowing out a first region of the active layer through a patterning process, wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.

Abstract: A mask plate comprises a light transmitting region; a light absorbing region; and a light reflecting region provided in the light absorbing region on one side of the mask plate. An exposing method using the mask plate comprises placing a first substrate coated with a first photosensitive resist layer under and parallel to the mask plate; having first light vertically strike on an upper surface of the mask plate from above, pass through the light transmitting region of the mask plate, and strike on the first photosensitive resist layer; placing a second substrate coated with a second photosensitive resist layer under and parallel to the mask plate; and having second light reflected by the lens device onto the surface of the mask plate where the light reflecting region is provided, then reflected by the light reflecting region and strike on the second photosensitive resist layer.

Abstract: The embodiments of the present invention provide a method of fabricating an array substrate, including steps of funning a thin film transistor, a pixel electrode and a common electrode line, wherein the step of forming the thin film transistor includes steps of forming patterns of a gate, a gate insulation layer, a semiconductor layer, an etch stop layer, a source and a drain, and the gate and the common electrode line are formed in the same layer. In the method, a gate insulation film and a semiconductor film are sequentially formed, and a pattern including the semiconductor layer is formed by one patterning process; and then an etch stop film is formed, and as pattern including the gate insulation layer and the etch stop layer is formed by one patterning process.

Abstract: An array substrate and a manufacturing method thereof as well as a display panel are provided. The manufacturing method comprises: forming a pattern including a scanning line (32) and a spacer base (33) on a same layer of a substrate (31); forming a gate insulating layer (34); forming a pattern including an active layer (35), a data line, a source electrode and a drain electrode; forming a passivation layer (36); sequentially etching the passivation layer (36) and the gate insulating layer (34) through a dry etching method to form a via hole (38) exposing the spacer base (33), and inducing materials generated from an etching process in a reaction cavity to deposit on a surface of the spacer base (33) through an electric field formed by the spacer base (33) exposed in the via hole (38) and etching gas adopted in the etching process, to form a spacer (39).

Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.

Abstract: Embodiments of the invention disclose an array substrate and a method for manufacturing the same, and a display device. The method for manufacturing an array substrate comprising: forming a gate metal layer, wherein the gate metal layer comprises gate lines; film-forming an active layer and film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after film-forming the active layer and before film-forming the signal line metal layer, the method further comprising: hollowing out a first region of the active layer through a patterning process, wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.

Abstract: An array substrate, comprising a display region and a GOA region. In the GOA region, a gate metal electrode, a gate insulating layer, an active layer, a transition layer, and a source-drain metal electrode are formed in sequence from bottom to top, and a via hole is provided penetrating the transition layer, the active layer and the gate insulating layer, the source-drain metal electrode is electrically connected to the gate metal electrode through the via hole; and at an edge of the via hole, there is formed an angle opening upward at edges of the transition layer and the active layer. There are further disclosed a manufacturing method of the array substrate and a display device provided with the array substrate.

Abstract: Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel.

Abstract: Disclosed are a TFT array substrate, a method for fabricating the same and a display device. The TFT array substrate includes a plurality of pixel units, each of the plurality of pixel units includes a common electrode (9). The common electrode (9), is comb-shaped, and includes a plurality of strip electrodes and a plurality of slits. Each of the strip electrodes is configured for reflecting light incident on the strip electrode, and each of the slits is configured for transmitting light incident on the slit. As the comb-shaped common electrode with both a reflective region and a transmissive region is formed through a single patterning process, the fabrication process is simplified and the fabrication cost and difficulty are reduced.

Abstract: An array substrate comprises a first metal layer in which first signal lines are disposed; a second metal layer in which second signal lines are disposed; an insulation layer provided between the first and second metal layers. A repairing line is provided in edge regions of the second metal layer and insulated from the second signal lines, and the repairing line comprises a first longitudinal portion, a second longitudinal portion and a transverse portion, the first longitudinal portion is electrically connected to the second longitudinal portion by the transverse portion. A projection of the first longitudinal portion in a plane of the first metal layer intersects with one end of each of the first signal lines, and a projection of the second longitudinal portion in the plane of the first metal layer intersects with the other end of each of the first signal lines.

Abstract: A new and distinct Camellia L. plant named ‘Pink Cascade’, characterized by its lanceolate leave shape, the width of its leaves measuring at about 1.8 cm to about 2.2 cm, its cascade stem shape, its flower stage at early March to early April, its light pink flower color, its single flower shape, and its diameter of the flower measuring at about 2 cm to about 4 cm.