Abstract: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Abstract: In accordance with the objectives of the invention a new water soluble negative photoresist is provided for packing-and-unpacking (PAU) processing steps.

Abstract: A system and method for automatic SPC chart generation including a storage device and a data acquisition module. The storage device stores a chamber management tree, a recipe window management tree, a parameter configuration table and multiple chart profile records. The data acquisition module, which resides in a memory, acquires multiple process events and parameter values corresponding to the process events and a process parameter, selects a relevant statistical algorithm, calculates a statistical value by applying the statistical algorithm to the parameter values, creates a new chart profile record and a parameter statistics record therein if the chart profile record is absent, and stores the statistical values and measured time in the parameter statistics record.

Abstract: A method is provided for the creation of contact holes. The invention provides two masks. The first mask, referred to as the packed mask, comprises the desired contact holes, which are part of the creation of a semiconductor device. To the packed mask are added padding holes in order to increase the hole density of the packed mask. An insulation layer is formed to protect the first layer of material. The second mask, referred to an the unpacking mask, comprises openings at the same locations as the locations of the padding holes of the first mask, the openings provided in the second mask have slightly larger dimensions than the padding holes of the first mask. A first exposure is made using the packed mask, a second exposure of the same surface area is made using the unpacking mask. The unpacking mask is used to selectively cover the padding contact holes, resulting in the final image.

Abstract: A method for reducing a critical dimension of a photoresist pattern while improving a line spacing between distal end portions of pattern lines wherein the method includes providing a substrate including an overlying resist; exposing the resist to an activating light source; baking the resist in a first baking process followed by developing the resist in a first development process to form a first resist pattern; then baking the first resist pattern in a second baking process followed by developing the first resist pattern in a second development process to form a second resist pattern having reduced dimensions; and, then dry trimming the second resist pattern to form a final resist pattern with reduced dimensions compared to the second resist pattern.

Abstract: A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.

Abstract: A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.

Abstract: An apparatus for fault detection and classification (FDC) specification management including a storage device and a process module. The storage device stores a specification management record and a chart profile record. The specification management record stores statistical algorithm settings of a parameter and the chart profile record stores chart frame and alarm condition information. The process module, which resides in a memory, receives a manipulation message corresponding to the specification management record, and accordingly manipulates the chart profile record.

Abstract: A system and method for automatic SPC chart generation including a storage device and a data acquisition module. The storage device stores a chamber management tree, a recipe window management tree, a parameter configuration table and multiple chart profile records. The data acquisition module, which resides in a memory, acquires multiple process events and parameter values corresponding to the process events and a process parameter, selects a relevant statistical algorithm, calculates a statistical value by applying the statistical algorithm to the parameter values, creates a new chart profile record and a parameter statistics record therein if the chart profile record is absent, and stores the statistical values and measured time in the parameter statistics record.

Abstract: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Abstract: A method for forming dual damascene structures within a semiconductor device utilizes a plug material that is soluble in alkaline developers such as 2.38 wt % TMAH. The plug material is introduced into openings initially formed in a dielectric film and extends up to at least the top surface of the dielectric film. The plug material is polymeric in nature and is baked to cross link the polymeric material. The dielectric layer with openings filled with the cross-linked plugged material is patterned and etched to produce dual damascene openings.

Abstract: A method is provided for the creation of contact holes. The invention provides two masks. The first mask, referred to as the packed mask, comprises the desired contact holes, which are part of the creation of a semiconductor device. To the packed mask are added padding holes in order to increase the hole density of the packed mask. An insulation layer is formed to protect the first layer of material. The second mask, referred to an the unpacking mask, comprises openings at the same locations as the locations of the padding holes of the first mask, the openings provided in the second mask have slightly larger dimensions than the padding holes of the first mask. A first exposure is made using the packed mask, a second exposure of the same surface area is made using the unpacking mask. The unpacking mask is used to selectively cover the padding contact holes, resulting in the final image.

Abstract: A method is provided for removing sidelobes that are formed when patterning a positive photoresist layer with an Att. PSM, Alt. PSM or a binary mask with scattering bars. A water soluble negative tone photoresist is coated over the positive photoresist pattern and is exposed through a mask having small islands that correspond in shape, size and location to the small holes in the mask used to pattern the positive tone photoresist. After development, exposed negative tone photoresist covers sidelobes formed by the positive tone process. The negative tone photoresist functions as a mask for a subsequent etch transfer of the positive tone pattern into the substrate. A method of aligning openings in a positive tone pattern over the same openings in a negative tone pattern is also useful in preventing sidelobes in the positive tone photoresist from being transferred into the substrate.

Abstract: A method and system is disclosed for selectively forming a pattern for making openings in a substrate. A first set of openings are formed in a first photoresist layer coated on the substrate using a first mask. A developing bottom antireflective coating (BARC) layer is then formed over the first photoresist with the openings filled therewith. A second photoresist layer is formed over the BARC layer. A second set of openings are formed in the second photoresist layer using a second mask exposing the BARC layer directly underneath. The exposed part of the BARC layer is then removed. Subsequently, one or more openings of the first set in the first photoresist layer, after the exposed part of the BARC layer filled therein is removed, are used for forming the openings in the substrate.

Abstract: A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.

Abstract: A primer tank having a nozzle assembly which uniformly distributes nitrogen or other vapor-generating gas against a primer liquid in the tank to generate a primer vapor for the priming of a semiconductor wafer substrate. The nozzle assembly includes a conduit to which is confluently attached a nozzle head having a nozzle plate. Multiple openings are provided in the nozzle plate to substantially uniformly distribute nitrogen or other inert gas against the surface of the primer liquid over a large area to generate a primer mist from the primer liquid and substantially reduce the formation of primer droplets in the tank.

Abstract: A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

Abstract: In accordance with the objectives of the invention a new water soluble negative photoresist is provided for packing-and-unpacking (PAU) processing steps.

Abstract: A method is provided for removing sidelobes that are formed when patterning a positive photoresist layer with an Att. PSM, Alt. PSM or a binary mask with scattering bars. A water soluble negative tone photoresist is coated over the positive photoresist pattern and is exposed through a mask having small islands that correspond in shape, size and location to the small holes in the mask used to pattern the positive tone photoresist. After development, exposed negative tone photoresist covers sidelobes formed by the positive tone process. The negative tone photoresist functions as a mask for a subsequent etch transfer of the positive tone pattern into the substrate. A method of aligning openings in a positive tone pattern over the same openings in a negative tone pattern is also useful in preventing sidelobes in the positive tone photoresist from being transferred into the substrate.

Abstract: The present invention provides a novel ammonium salt of an organic acid. When the salt is used as a base additive for a chemically amplified resist, the environmental stability of the resist can be enhanced, and the T-top phenomenon can be effectively prevented. In addition, the line width change caused by acid diffusion can be prevented, and the E0 value of the resist can be decreased.