Abstract: A printhead with a number of memristors and a parallel current distributor is described. The printhead includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The printhead also includes a number of memristor cells. Each memristor cell includes a memristor to store information and a multiplexing component to select a memristor. The printhead also includes and at least one current distributor connected in parallel to a number of memristor cells.

Abstract: A fast erasing memristor includes an active region, a resistive heater, and a dielectric sheath. The active region has a switching layer coupled between a first conducting layer and second conducting layer. The resistive heater is coupled to the active region to provide heat to the active region. The dielectric sheath separates the active region and the resistive heater.

Abstract: An example memristor includes a first conductive layer, a switching layer, and a second conductive layer. The first conductive layer may include a first conductive material and a second conductive material. The second conductive material may have a higher diffusivity than the first conductive material. The switching layer may be coupled to the first conductive layer and may include a first oxide having the first conductive material and a second oxide having the second conductive material. The second conductive layer may be coupled to the switching layer.

Abstract: A resistive memory array includes a plurality of resistive memory devices. A sneak path current in the resistive memory array is reduced when a negative temperature coefficient of resistance material is incorporated in series with a negative differential resistance selector that is in series with a memristor switching material at a junction formed at a cross-point between two conductors of one of the plurality of resistive memory devices.

Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.

Abstract: A superlinear selector includes a first electrode, a second electrode, and an active layer coupled in series between the first electrode and the second electrode. The active layer includes a superlinear electrical conductor and an electrical insulator. One of the superlinear electrical conductor and the electrical insulator forms a matrix in which the other of the superlinear electrical conductor and the electrical insulator is dispersed.

Abstract: A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to form an electrical series connection through the n-type layer, the intrinsic layer, and the p-type layer.

Abstract: A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a composite dielectric material of a first dielectric material, a second dielectric material that is different from the first dielectric material, and a dopant material including a cation having a migration rate faster than the oxygen or the nitrogen elements of the memristor. The first dielectric material and the second dielectric material are present in a ratio ranging from 1:9 to 9:1, and a concentration of the dopant material in the composite dielectric material ranges from about 1% up to 50%.

Abstract: A method of forming a multi-layered selector of a memory cell is described. In the method, a memory element of the memory cell is formed. The memory element stores information. A multi-layered selector of the memory cell is formed by alternating deposition of at least a dielectric layer and a first diffusion layer. The first diffusion layer includes fast diffusive ions. The multi-layered selector is coupled to the memory element in a memory cell.

Abstract: A method of obtaining a dot product using a memristive dot product engine with a nulling amplifier includes applying a number of programming voltages to a number of row lines within a memristive crossbar array to change the resistance values of a corresponding number of memristors located at intersections between the row lines and a number of column lines. The method also includes applying a number of reference voltages to the number of the row lines and applying a number of operating voltages to the number of the row lines. The operating voltages represent a corresponding number of vector values. The method also includes determining an array output based on a reference output and an operating output collected from the number of column lines.

Abstract: Provided in one example is an article. The article including: a first electrode; a switching layer disposed over at least a portion of the first electrode, the switching layer including a metal oxide; and a second electrode disposed over at least a portion of the switching layer. The first electrode, the switching layer, and the second electrode are parts of a resistive random-access memory, and one or both of the first electrode and the second electrode is a part of a layer of a printed circuit board.

Abstract: A negative differential resistance (NDR) device for non-volatile memory cells in crossbar arrays is provided. Each non-volatile memory cell is situated at a crosspoint of the array. Each non-volatile memory cell comprises a switching layer in series with an NDR material containing fast diffusive atoms that are electrochemically inactive. The switching layer is positioned between two elec-trodes.

Abstract: A device according to examples of the present disclosure includes a crossbar array including a cell. The cell includes a first resistance switch and a second resistance switch connected in series with the first resistance switch. The first and second resistance switches have different switching characteristics. One of the first and second resistance switches may act as a switch, while the other of the first and second resistance switches may weight the switching behavior of the one that acts as the switch.

Abstract: A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set of logic indicators. Each first memristor is grouped with a corresponding second memristor during a memory read operation to generate a representative logic indicator.

Abstract: In an example, a printhead includes a memristor, in which the memristor may include a first electrode, a second electrode positioned in a crossed relationship with the first electrode to form a junction, and a switching element positioned at the junction between the first electrode and the second electrode, in which the switching layer includes a via formed in the switching element to reduce an area of the switching element.

Abstract: An example apparatus includes a crossbar array of signal lines and control lines. The example apparatus also includes an input controller in circuit with the control lines. The input control is to select one of the control lines. The example apparatus also includes first resistive elements connected between corresponding ones of the control lines and corresponding ones of the signal lines. The first resistive elements have first conductances set to operate as a matrix of probabilities that define a fixed transition kernel of a Markov Chain. The example apparatus also includes second resistive elements in circuit with the signal lines. The second resistive elements have second conductances set to select one of the signal lines exclusive of others of the signal lines based on a subset of the probabilities in the matrix of the probabilities.

Abstract: A printhead with a number of memristors and a parallel current distributor is described. The printhead includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The printhead also includes a number of memristor cells. Each memristor cell includes a memristor to store information and a multiplexing component to select a memristor. The printhead also includes and at least one current distributor connected in parallel to a number of memristor cells.

Abstract: A method of sensing an output signal in a crossbar array is described. In the method, a selecting voltage is applied to a target memory element of the crossbar array. Also in the method, a non-selecting voltage is applied to non-target memory elements of the crossbar array. Further in the method, a target output that is associated with the target memory element is isolated, with sensing circuitry, from a sneak output based on a time delay between arrival of the target output and the sneak output and the target output is sensed.

Abstract: A system for asymmetrically selecting a memory element is described. The system includes a number of memory cells in a crossbar array. Each memory cell includes a memory element to store information. The memory element is defined as an intersection between a column electrode and a row electrode of the crossbar array. Each memory cell also includes a selector to select a target memory element by relaying a first selecting voltage to a column electrode that corresponds to the target memory element and relaying a second selecting voltage to a row electrode that corresponds to the target memory element. The system also includes a controller to pass a first standing voltage to column electrodes of the crossbar array and to pass a second standing voltage to row electrodes of the crossbar array. The first standing voltage is different than the second standing voltage.

Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.