Patents by Inventor Jianjun Guo

Jianjun Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250023319
    Abstract: A laser device and a laser projection equipment are provided.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Inventors: Zinan Zhou, Yao LU, Zhaoshi GUO, Jianjun LI
  • Patent number: 12134035
    Abstract: A cloud native 3D scene game and method thereof, including: initiating a game request by one or more users to a cloud server through a game client, creating and starting one corresponding game process according to the game request of the one or more users by the cloud server, and processing the game data of the one or more users at the same time by the game process. The invention has the advantages that: game data of multiple users are processed through one game process, and multiple virtual cameras are controlled to generate corresponding game screens for different users at the same time in one game process which can obviously reduce consumption of server resources and reduce the number of the servers, meanwhile, the fluency of game screens can be guaranteed, the user experience can be improved, and the interaction fluency among different users can be improved.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: November 5, 2024
    Assignee: WELLINK TECHNOLOGIES CO., LTD.
    Inventors: Huaqing Sun, Jianjun Guo
  • Publication number: 20240362747
    Abstract: A method for generating an image super-resolution data set, an image super-resolution model and a training method. The method for generating an image super-resolution data set comprises steps of: S101: constructing a high-resolution image set; S102: performing image blind degradation processing on all high-resolution images HR1 to obtain an LR1-HR1 data set; S103: training a first model with the LR1-HR1 data set to obtain a model parameter of the first model and saving the model parameter; S104: constructing a low-resolution image set; and S105: inputting all low-resolution images LR2 into the first model to obtain an LR2-SR2 data set after inference by the first model. Using the LR2-SR2 data set of the present disclosure, training can be performed on a model with a relatively simple structure, the learning speed is fast, and the trained model has strong generalization ability.
    Type: Application
    Filed: December 11, 2023
    Publication date: October 31, 2024
    Inventor: Jianjun GUO
  • Publication number: 20240313028
    Abstract: An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array.
    Type: Application
    Filed: March 25, 2024
    Publication date: September 19, 2024
    Applicant: Eastern Blue Technologies, Inc.
    Inventors: Jianjun Guo, Yin Qian
  • Patent number: 12014103
    Abstract: Game screen rendering based on multiple graphics cards. Recognizing M physical graphics cards on a physical host, determining a rendering task and segmenting it into at least one rendering part; determining a target physical graphics card according to the at least one rendering part, wherein the target physical graphics card is one or more of the M physical graphics cards; rendering the at least one rendering part through the target physical graphics card; and outputting a rendering result through an output device.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: June 18, 2024
    Assignee: WELLINK TECHNOLOGIES CO., LTD.
    Inventors: Yuexin Wu, Jianjun Guo, Huaqing Sun
  • Patent number: 11942503
    Abstract: An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: March 26, 2024
    Assignee: EASTERN BLUE TECHNOLOGIES, INC.
    Inventors: Jianjun Guo, Yin Qian
  • Publication number: 20230364866
    Abstract: A three-dimensional structured multi-level interlocking structure and a preparation method thereof, the multi-level interlocking structure comprises: a first interlocking structure comprising a first bonding component, first bonding troughs and first macrostmctures alternately positioned on the surface of the first bonding component, and a second interlocking structure comprising a second bonding component, second bonding troughs and second macrostmctures alternately positioned on the surface of the second bonding component, the first macrostructures are aligned with the second bonding trough, and the second macrostmctures are aligned with the first bonding trough; and the first macrostructure has a first end away from the first bonding component and the second macrostructure has a first end away from the second bonding component, the first ends of the first macrostructure and the second macrostructure comprise a top plane, the first end of the first macrostructure extends past the top plane of the second mac
    Type: Application
    Filed: January 12, 2022
    Publication date: November 16, 2023
    Applicants: The Boeing Company, Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences
    Inventors: Jianjun Guo, Yifan Zhang, Zhixiang Li, Gaojie Xu
  • Publication number: 20220193547
    Abstract: Methods and systems are presented for game screen rendering based on multiple graphics cards, for recognizing M physical graphics cards on a physical host, determining a rendering task and segmenting it into at least one rendering part; determining a target physical graphics card according to the at least one rendering part, wherein the target physical graphics card is one or more of the M physical graphics cards; rendering the at least one rendering part through the target physical graphics card; and outputting a rendering result through an output device.
    Type: Application
    Filed: January 7, 2021
    Publication date: June 23, 2022
    Applicant: WELLINK TECHNOLOGIES CO., LTD.
    Inventors: Yuexin WU, Jianjun GUO, Huaqing SUN
  • Publication number: 20220193540
    Abstract: Methods and systems are presented for a cloud native 3D scene game, for initiating a game request by one or more users to a cloud server through a game client, creating and starting one corresponding game process according to the game request of the one or more users by the cloud server, and processing the game data of the one or more users at the same time by the game process. A cloud server is used for creating the game process for a plurality of users.
    Type: Application
    Filed: September 8, 2020
    Publication date: June 23, 2022
    Applicant: WELLINK TECHNOLOGIES CO., LTD.
    Inventors: Huaqing SUN, Jianjun GUO
  • Patent number: 11197656
    Abstract: The present invention provides a pulsed Doppler ultra-high spectral resolution imaging processing method and processing system. The method includes: acquiring IQ signals corresponding to N sampling points respectively on each scan line; in a fast time direction, performing wall filtering processing to form an IQ signal wall filtering sequence; performing FFT on each sampling point in the IQ signal wall filtering sequence in a slow and a fast time direction, respectively, to obtain an energy distribution matrix at different frequency shifts; acquiring a velocity distribution matrix; and retrieving a velocity sequence for display, querying the velocity distribution matrix and the energy distribution matrix according to the velocity sequence, and acquiring an energy sequence corresponding to the velocity sequence for displaying a final spectrum. When a transmit signal bandwidth is wider or a scatterer velocity is faster, the velocity resolution is greatly guaranteed.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: December 14, 2021
    Assignee: VINNO TECHNOLOGY (SUZHOU) CO., LTD
    Inventors: Jianjun Guo, Huiren Chen
  • Publication number: 20210327946
    Abstract: An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array.
    Type: Application
    Filed: May 8, 2019
    Publication date: October 21, 2021
    Inventors: Jianjun Guo, Yin Qian
  • Patent number: 10779778
    Abstract: The present approach relates to the use of detector elements (i.e., reference detector pixels) positioned under septa of an anti-scatter collimator. Signals detected by the reference detector pixels may be used to correct for charging-sharing events with adjacent pixels and/or to characterize or correct for focal spot misalignment either in real time or as a calibration step.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: September 22, 2020
    Assignee: General Electric Company
    Inventors: Xue Rui, Geng Fu, Yannan Jin, Jianjun Guo, Peter Michael Edic, Brian David Yanoff
  • Patent number: 10772609
    Abstract: An ultrasonic imaging processing method based on RF data includes the following steps: S1, receiving echo signals which are obtained by sending ultrasound signals; S2, beamforming the echo signals; S3, obtaining the RF data of the echo signals; and S4, directly conducting an ultrasonic imaging process based on the obtained RF data in order to obtain a target image. The ultrasonic imaging processing method and system based on the RF data according to the present application directly conduct ultrasonic imaging treatment based on the obtained RF data of the echo signals in order to obtain the target image.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: September 15, 2020
    Assignee: VINNO TECHNOLOGY (SUZHOU) CO., LTD.
    Inventors: Huiren Chen, Tao Ling, Jianjun Guo, Dajun Yin, Shui Xi
  • Patent number: 10686003
    Abstract: Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: June 16, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Biju Jacob, Habib Vafi, Brian David Yanoff, Jeffery Jon Shaw, Jianjun Guo
  • Patent number: 10571579
    Abstract: A detector is described having readout electronics integrated in the photodetector layer. The detector may be configured to acquire both energy-integrated and photon-counting data. In one implementation, the detector is also configured with control logic to select between the jointly generated photon-counting and energy-integrated data.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: February 25, 2020
    Assignee: General Electric Company
    Inventors: Yannan Jin, Geng Fu, Peter Michael Edic, Brian David Yanoff, Jianjun Guo
  • Patent number: 10564299
    Abstract: A SiPM tile includes SiPM arrays on a detector die, each of the SiPM arrays including a first plurality of microcells and a second plurality of reference microcells dispersed on the die, each reference microcell including an optically-opaque mask, a readout circuit each including a respective charge sensitive amplifier (CSA) connected to one of the reference microcells, each CSA configured to accumulate the dark current of the reference microcell during a selected time window, a hybrid temperature control circuit configured to receive an output signal from each CSA, and to determine the real-time temperature of the die based on the received output signal, to provide the real-time temperature to a temperature compensation and correction control unit that adjusts a cooling/heating system flow provided to the die, the adjustment based on the real-time temperature. A method for compensating the operating temperature variation of the SiPM tile is also disclosed.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: February 18, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Geng Fu, Jianjun Guo
  • Patent number: 10466368
    Abstract: A silicon photomultiplier (SiPM) based detection system includes a plurality of scintillators, SiPMs, a front end circuit, adjustment circuits, and an energy and position processing unit. The SiPMs have a non-linear response to energy deposition corresponding to radiation detection. The adjustment circuit is configured to receive an analog signal from SiPMs, and to provide an adjusted analog signal, which is configured to simulate a signal corresponding to a linear response. The energy and position processing unit utilizes the adjusted signal to provide energy and position information of detected events in the detector block.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: November 5, 2019
    Assignee: General Electric Company
    Inventors: Geng Fu, Hua Qian, Hao Lai, Jianjun Guo, Adrian Ivan, Brian Yanoff
  • Patent number: 10371835
    Abstract: A silicon photomultiplier array including a plurality of microcells arranged in rows and columns. A plurality of circuit traces connecting microcell output ports to the array pixel output port, with one or more impedance matching networks connected to at least one of the circuit traces. The impedance matching networks can be connected between each row circuit trace and the pixel output port. Impedance matching networks can be located between junctions of adjacent microcell output ports and row circuit traces.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: August 6, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Jianjun Guo, Adrian Ivan, Sergei Ivanovich Dolinsky, Geng Fu
  • Patent number: 10283557
    Abstract: Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: May 7, 2019
    Assignee: General Electric Company
    Inventors: Biju Jacob, Habib Vafi, Brian David Yanoff, Jeffery Jon Shaw, Jianjun Guo
  • Patent number: 10261201
    Abstract: A method for determining depth-of-interaction correction in a PET system. The method includes modifying crystal and readout configuration to improve depth-dependent arrival profile of scintillation photons, creating a photon dispersion model within a scintillator crystal, measuring photon arrival profile of individual gamma ray event, deriving an estimated depth-of-interaction, and deriving a gamma ray event time based on a time stamp corrected with the estimated depth-of-interaction. The method further includes modeling dispersion at different depths of interaction within the scintillator crystal, providing a reflector layer to delay back-reflected photons, providing two respective readouts for the same gamma ray event from two respective pixels optically coupled by a backside reflector or modified crystal configuration, calculating a time difference of the photon arrival at the two pixels, and estimating the depth-of-interaction by applying a statistical weighting.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: April 16, 2019
    Assignee: General Electric Company
    Inventors: Geng Fu, Floribertus P M Heukensfeldt Jansen, Jianjun Guo, Sergei Ivanovich Dolinsky