Abstract: A detector panel is described having readout circuitry integrated with the photodetectors, such as in the light imager panel. The detector is useful in high spatial resolution and low-dose or low-signal imaging contexts and may be used in adaptive 2D binning configurations. Adaptive binning of detector elements may be accomplished using control logic and X-ray intensity detector circuitry capable of assessing an incident X-ray intensity and controlling binning of an associated group of detector elements.

Abstract: A detector is described having readout electronics integrated in the photodetector layer. The detector may be configured to acquire both energy-integrated and photon-counting data. In one implementation, the detector is also configured with control logic to select between the jointly generated photon-counting and energy-integrated data.

Abstract: A silicon photomultiplier array including a plurality of microcells arranged in rows and columns. A plurality of circuit traces connecting microcell output ports to the array pixel output port, with one or more impedance matching networks connected to at least one of the circuit traces. The impedance matching networks can be connected between each row circuit trace and the pixel output port. Impedance matching networks can be located between junctions of adjacent microcell output ports and row circuit traces.

Abstract: Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.

Abstract: Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.

Abstract: A commutator (10) comprising a plurality of commutator bars (12) formed from a graphite structure (30) and a metal sheet (20) having soldered to the graphite structure (30) includes a brazing process followed by a soldering process. The brazing process includes applying a brazing material the graphite structure (30) and brazing at an elevated temperature to form a brazing layer (40). The soldering process includes applying a solder material to the brazing layer (40), placing the metal sheet (20) on the solder material, and soldering to form a solder layer (50) affixing the metal sheet (20) to the graphite structure (30). A plurality of grooves (70) are cut in the graphite structure (30) and the metal sheet (20) to form the commutator bars (12) arranged in an intermittent ring or circle.

Abstract: A digital X-ray detector is provided. The digital X-ray detector includes multiple pixels, each pixel including a pinned photodiode, and multiple readout channels coupled to each pinned photodiode, wherein each readout channel includes at least one charge-storage capacitor, an amplifier, and a transfer gate. The digital X-ray detector also includes control circuitry coupled to each pixel of the multiple pixels and configured to selectively control a flow of photocharge generated by each pinned photodiode to a respective at least one charge-storage capacitor of each respective readout channel via control of each respective transfer gate of each respective readout channel.

Abstract: Some embodiments are associated with an input signal comprising a first and a second photon event incident on a photon-counting semiconductor detector. A relatively slow charge collection shaping amplifier may receive the input signal and output an indication of a total amount of energy associated with the superposition of the first and second events. A relatively fast charge collection shaping amplifier may receive the input signal and output an indication that is used to allocate a first portion of the total amount of energy to the first event and a second portion of the total amount of energy to the second event.

Abstract: An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines—selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.

Abstract: An imager including sub-imager pixel arrays having a plurality of four-side buttable imagers distributed on a substrate and an on-chip digitizing readout circuit. Pixel groupings formed from among the plurality of four-side buttable imagers. The readout electronics including a buffer amplifier for each of the pixel groupings and connected to respective outputs of each four-side buttable imager of the pixel grouping. A plurality of shared analog front ends, each shared analog front end connected to respective multiple buffer amplifiers from among the plurality of pixel groupings. An analog-to-digital converter located at a common centroid location relative to the plurality of shared analog front ends, the analog-to-digital converter having a fully addressable input selection to individually select an output from each of the plurality of shared analog front ends. An output of the analog-to-digital converter connected to a trace on a back surface of the wafer substrate by a through-substrate-via.

Abstract: Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a photosensor may include a sensing element; and readout electronics, wherein the sensing element is AC coupled to the readout electronics. In some embodiments, a solid state photomultipler may include a microcell having; a sensing element; and readout electronics, wherein the sensing element is AC coupled to the readout electronics.

Abstract: A photon detector having an optical transparent plate and photodiode array interconnected by an optical light guide array. The optical light guide array including elements providing a transmission line between the optical transparent plate and the photodiode array, where the position of one or more optical light guide elements is formed to adjust for a miss-registered photodiode individual element.

Abstract: A silicon photomultiplier array of microcells including a photon avalanche diode and an electronic circuit configured to provide a first one-shot pulse and a second one-shot pulse based on a detected current flowing through the photon avalanche diode. The microcells arranged in rows and columns with each microcell of a respective row connected to a respective row data bus connected to a row counter configured to count one or more first one-shot pulses for a predetermined time period, a pixel adder configured to sum the count, and a digital-to-analog converter connected to the pixel adder to convert sum to an analog signal representative of an energy readout. A timing logic circuit configured to provide a validation signal to a counter control logic circuit, and the counter control logic circuit configured to provide one of a start signal, a stop signal, and a reset signal to the row counter.

Abstract: An imager including sub-imager pixel arrays having a plurality of four-side buttable imagers distributed on a substrate and an on-chip digitizing readout circuit. Pixel groupings formed from among the plurality of four-side buttable imagers. The readout electronics including a buffer amplifier for each of the pixel groupings and connected to respective outputs of each four-side buttable imager of the pixel grouping. A plurality of shared analog front ends, each shared analog front end connected to respective multiple buffer amplifiers from among the plurality of pixel groupings. An analog-to-digital converter located at a common centroid location relative to the plurality of shared analog front ends, the analog-to-digital converter having a fully addressable input selection to individually select an output from each of the plurality of shared analog front ends. An output of the analog-to-digital converter connected to a trace on a back surface of the wafer substrate by a through-substrate-via.

Abstract: A digital X-ray detector is provided. The digital X-ray detector includes multiple pixels, each pixel including a pinned photodiode, and multiple readout channels coupled to each pinned photodiode, wherein each readout channel includes at least one charge-storage capacitor, an amplifier, and a transfer gate. The digital X-ray detector also includes control circuitry coupled to each pixel of the multiple pixels and configured to selectively control a flow of photocharge generated by each pinned photodiode to a respective at least one charge-storage capacitor of each respective readout channel via control of each respective transfer gate of each respective readout channel.

Abstract: Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include an epitaxial layer, a high voltage region formed in the epitaxial layer, a low voltage region formed in the epitaxial layer, and an intermediate region disposed between the high voltage region and low voltage region, wherein the high voltage region is electrically coupled to the low voltage region via the intermediate region, and wherein at least a portion of the epitaxial layer is disposed between the high voltage region and intermediate region and between the low voltage region and the intermediate region.

Abstract: Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include a plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of subpixels; and a first set of buffer amplifiers, wherein each buffer amplifier of the first set of buffer amplifiers is respectively coupled to a subpixel of the plurality of subpixels.

Abstract: A silicon photomultiplier array of microcells including a photon avalanche diode and an electronic circuit configured to provide a first one-shot pulse and a second one-shot pulse based on a detected current flowing through the photon avalanche diode. The microcells arranged in rows and columns with each microcell of a respective row connected to a respective row data bus connected to a row counter configured to count one or more first one-shot pulses for a predetermined time period, a pixel adder configured to sum the count, and a digital-to-analog converter connected to the pixel adder to convert sum to an analog signal representative of an energy readout. A timing logic circuit configured to provide a validation signal to a counter control logic circuit, and the counter control logic circuit configured to provide one of a start signal, a stop signal, and a reset signal to the row counter.

Abstract: A multichannel application specific integrated circuit (ASIC) for interfacing with an array of photodetectors in a positron emission tomography (PET) imaging system includes a front end circuit configured to be coupled to the photodetectors and to receive discrete analog signals therefrom. The ASIC further includes a time discriminating circuit operably coupled to the front end circuit and configured to generate a hit signal based on a combination of the discrete analog signals, and an energy discriminating circuit operably coupled to the front end circuit and configured to generate a summed energy output signal based on each of the discrete analog signals and summed row and column output signals based on each of the discrete analog signals. The summed energy output signal represents an energy level of the detected radiation in the array of photodetectors, and the summed row and column output signals represent a location of the detected radiation.

Abstract: A compensating current is applied at one or more points in a signal processing path to compensate for one or both of a dark or offset current present in an input signal. In certain implementations, the dark or offset current is present in a signal generated by a photomultiplier device. The dark or offset current may be monitored in an output of the signal processing path and, the monitoring being used to determine how much compensation is needed in the signal processing path and to allocate where in the signal processing path the compensation current will be applied.