Patents by Inventor Jianping Xu

Jianping Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7088138
    Abstract: A CML XOR logic circuit is provided that includes a pair of pull-up transistors, a pair of current source transistors and a logic switch network coupled between the pull-up transistors and the current source transistors. The logic switch network including a plurality of transistors divided into a first branch, a second branch and a third branch. A tail current flows through the first branch, the second branch or the third branch based on at least two input signals to the plurality of transistors.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Jianping Xu, Fabrice Paillet, Tanay Karnik
  • Patent number: 7088191
    Abstract: According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, David Rennie, Tanay Karnik, Jianping Xu
  • Publication number: 20060170481
    Abstract: In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted version of the first input signal. The apparatus further includes a second pair of transistors to receive the first input signal and the second input signal and to generate a second output signal that is a shifted version of the second input signal.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 3, 2006
    Inventors: Fabrice Paillet, David Rennie, Tanay Karnik, Jianping Xu
  • Publication number: 20060103479
    Abstract: According to some embodiments, a circuit includes a ring oscillator delay stage. The delay stage may include a first transistor, a second transistor, and an active inductor. A gate of the first transistor may receive a first input signal, a gate of the second transistor may receive a second input signal, a source of the second transistor may be coupled to a source of the first transistor, and the active inductor may be coupled to a drain of the first transistor.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 18, 2006
    Inventors: Fabrice Paillet, Tanay Karnik, Jianping Xu
  • Publication number: 20060071722
    Abstract: According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.
    Type: Application
    Filed: September 29, 2004
    Publication date: April 6, 2006
    Inventors: Fabrice Paillet, David Rennie, Tanay Karnik, Jianping Xu
  • Patent number: 7023023
    Abstract: An integrated circuit die includes optical interconnect ports on a first side and electrical interconnect ports on a second side.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: Tanay Karnik, Jianping Xu
  • Publication number: 20060067452
    Abstract: A clock and data recovery circuit is provided that includes a phase/frequency detector to receive input data and multiphase clock signals. The phase/frequency detector including a first set of flip-flop circuits each to sample the input data at one of the multiphase clock signals and each to output a sampled data, and a second set of flip-flop circuits to retime the sampled data based on a similar clock signal applied to each of the second set of flip-flop circuits.
    Type: Application
    Filed: September 24, 2004
    Publication date: March 30, 2006
    Inventors: Jianping Xu, Fabrice Paillet, Peter Hazucha, Tanay Karnik
  • Publication number: 20060061399
    Abstract: A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.
    Type: Application
    Filed: September 22, 2004
    Publication date: March 23, 2006
    Inventors: Jianping Xu, KyeHyung Lee, Fabrice Paillet, David Rennie, Tanay Karnik
  • Patent number: 7016354
    Abstract: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: March 21, 2006
    Assignee: Intel Corporation
    Inventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar
  • Publication number: 20060044010
    Abstract: A CML XOR logic circuit is provided that includes a pair of pull-up transistors, a pair of current source transistors and a logic switch network coupled between the pull-up transistors and the current source transistors. The logic switch network including a plurality of transistors divided into a first branch, a second branch and a third branch. A tail current flows through the first branch, the second branch or the third branch based on at least two input signals to the plurality of transistors.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 2, 2006
    Inventors: Jianping Xu, Fabrice Paillet, Tanay Karnik
  • Patent number: 6995605
    Abstract: A resonance suppression circuit is provided to suppress resonance on a power grid of a chip or die. The resonance suppression circuit may include a band-pass filter portion, a comparator portion, an amplification portion and a current dissipation portion. The band-pass filter portion may include an inverter coupled between two signal lines of the power grid. The comparator portion may sense voltage fluctuations at approximately the resonance frequency and trigger the current dissipation portion to turn ON and thereby change the frequency spectrum of the load current on the power grid to suppress the power grid resonance.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: February 7, 2006
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Jianping Xu, Gerhard Schrom, Tanay Karnik, Fabrice Paillet, Vivek K. De
  • Publication number: 20050269586
    Abstract: A light-emitting device and optical communication system based on the light-emitting device is disclosed. The light-emitting device is formed in a float-zone substrate. The light-emitting device includes on the substrate lower surface a reflective layer and on the upper surface spaced apart doped regions. The portion of the upper surface between the doped regions is textured and optionally covered with an antireflection coating to enhance light emission. The light-emitting device can operate as a laser or as a light-emitting diode, depending on the reflectivities of the antireflection coating and the reflective layer.
    Type: Application
    Filed: August 2, 2005
    Publication date: December 8, 2005
    Inventors: Donald Gardner, Tanay Karnik, Jianping Xu, Shekhar Borkar
  • Patent number: 6967515
    Abstract: A circuit to provide a differential signal output in response to a single-ended signal input, the circuit allowing for a wide common-mode input signal by providing complementary amplifier structures.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: November 22, 2005
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, David Rennie, Tanay Karnik, Jianping Xu
  • Patent number: 6958640
    Abstract: An apparatus and method for generating signals with improved timing resolution includes a delay cell configured to receive dual coupled differential input signals. The delay cell performs an interpolation function which smooths state transitions or other discontinuities that result from timing or phase offsets between the input signals. The interpolation function is performed by resistors which couple respective components of the differential inputs prior to traversing delay paths. A delay cell of this type has high supply noise rejection and a low output swing range, thereby making it suitable for a number of applications. One application includes a jitter noise generator which uses the delay cell to achieve improved timing resolution and which is not limited by a minimum delay of the cell. Another application uses the delay cell to form a coupled delay line.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: October 25, 2005
    Assignee: Intel Corporation
    Inventors: KyeHyung Lee, Jianping Xu, Fabrice Paillet, Tanay Karnik
  • Publication number: 20050232637
    Abstract: A laser driver for high speed interconnections may convert a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one. An optical signal thus produced may include an optical offset. An optical receiver may include a photo-detector to receive the optical signal and generate a current signal, which includes a corresponding current offset. A first amplifier stage converts the current signal to a voltage signal and a second amplifier stage generates a digital output from the voltage signal. One or more low-pass filters may be used to filter the digital output and generate a filtered offset signal for a differential amplifier to generate an offset cancellation signal. The offset cancellation signal may be provided to offset cancellation circuitry to remove the current offset from the current signal generated by the photo-detector.
    Type: Application
    Filed: December 30, 2004
    Publication date: October 20, 2005
    Inventors: Fabrice Paillet, Tanay Karnik, Jianping Xu, Donald Gardner
  • Publication number: 20050226279
    Abstract: One embodiment of a laser driver for high speed interconnections includes a buffered level shifter to shift the input voltage level to an appropriate level. In some embodiments the buffered level shifter may be tuned to provide a desired level shift with impedance matched to the driving load. Another embodiment converts a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one, wherein one or both of the bias mode and modulation mode may be adjusted, for example by a programmable control circuit or by an adaptive control circuit. Some embodiments also provide circuitry for reducing overshoot of the output signal.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Jianping Xu, Fabrice Paillet, Tanay Karnik
  • Publication number: 20050218972
    Abstract: A resonance suppression circuit is provided to suppress resonance on a power grid of a chip or die. The resonance suppression circuit may include a band-pass filter portion, a comparator portion, an amplification portion and a current dissipation portion. The band-pass filter portion may include an inverter coupled between two signal lines of the power grid. The comparator portion may sense voltage fluctuations at approximately the resonance frequency and trigger the current dissipation portion to turn ON and thereby change the frequency spectrum of the load current on the power grid to suppress the power grid resonance.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: Peter Hazucha, Jianping Xu, Gerhard Schrom, Tanay Karnik, Fabrice Paillet, Vivek De
  • Publication number: 20050212559
    Abstract: A circuit to provide a differential signal output in response to a single-ended signal input, the circuit allowing for a wide common-mode input signal by providing complementary amplifier structures.
    Type: Application
    Filed: March 24, 2004
    Publication date: September 29, 2005
    Inventors: Fabrice Paillet, David Rennie, Tanay Karnik, Jianping Xu
  • Patent number: 6924510
    Abstract: A light-emitting device and optical communication system based on the light-emitting device is disclosed. The light-emitting device is formed in a float-zone substrate. The light-emitting device includes on the substrate lower surface a reflective layer and on the upper surface spaced apart doped regions. The portion of the upper surface between the doped regions is textured and optionally covered with an antireflection coating to enhance light emission. The light-emitting device can operate as a laser or as a light-emitting diode, depending on the reflectivities of the antireflection coating and the reflective layer.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: August 2, 2005
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Tanay Karnik, Jianping Xu, Shekhar Y. Borkar
  • Publication number: 20050140412
    Abstract: An apparatus and method for generating signals with improved timing resolution includes a delay cell configured to receive dual coupled differential input signals. The delay cell performs an interpolation function which smooths state transitions or other discontinuities that result from timing or phase offsets between the input signals. The interpolation function is performed by resistors which couple respective components of the differential inputs prior to traversing delay paths. A delay cell of this type has high supply noise rejection and a low output swing range, thereby making it suitable for a number of applications. One application includes a jitter noise generator which uses the delay cell to achieve improved timing resolution and which is not limited by a minimum delay of the cell. Another application uses the delay cell to form a coupled delay line.
    Type: Application
    Filed: December 31, 2003
    Publication date: June 30, 2005
    Inventors: KyeHyung Lee, Jianping Xu, Fabrice Paillet, Tanay Karnik