Abstract: The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines).

Abstract: A digital signature collection and authentication system includes an ink pen having an ultrasonic transmitter that transmits ultrasonic energy to a plurality of ultrasonic receivers. A computer triangulates the location of the pen versus time to generate the signature shape, and to generate velocity and acceleration data. The pen also includes a pressure sensitive tip to record pressure applied to the pen tip. The pen also includes a higher frequency burst transmitter useful to generate a time reference, and to transmit the pressure information. The computer packetizes the shape, velocity, acceleration, and pressure data with a time stamp and an IP address or phone number, encrypts the packet and sends it to a host computer for authentication.

Abstract: A power management device for enabling multiply power sources to supply power to a load. The power management device includes a plurality of switches and a control logic. The plurality of switches are coupled to a plurality of power sources respectively and each switch coupled to each power source. The control logic is capable of selecting a set of switches among the plurality of switches to cooperate in a time-divided fashion to allow the power sources to provide power to the load. The set of switches is selected based on an electrical requirement of the load and an electrical condition of each switch.

Abstract: A digital signature collection and authentication system includes an ink pen having an ultrasonic transmitter that transmits ultrasonic energy to a plurality of ultrasonic receivers. A computer triangulates the location of the pen versus time to generate the signature shape, and to generate velocity and acceleration data. The pen also includes a pressure sensitive tip to record pressure applied to the pen tip. The pen also includes a higher frequency burst transmitter useful to generate a time reference, and to transmit the pressure information. The computer packetizes the shape, velocity, acceleration, and pressure data with a time stamp and an IP address or phone number, encrypts the packet and sends it to a host computer for authentication.

Abstract: A wireless coordinate input system for a display system includes a stylus that transmits ultrasonic energy to a plurality of ultrasonic receiving stations in a projection plane. In an embodiment, the stylus may include one ultrasonic transmitter used for determination of three-dimensional coordinates of the stylus relative to the projection plane. The stylus may also include a second ultrasonic transmitter controlled by a pressure-activated switch. When the stylus is pressed against the projection plane, the second transmitter turns on and is used for determination of two-dimensional coordinates of the stylus in the projection plane. The stylus may also include a higher frequency burst transmitter used to generate a time reference. One or more of the ultrasonic receiving stations may also include an ultrasonic transmitter for calibration.

Abstract: In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted version of the first input signal. The apparatus further includes a second pair of transistors to receive the first input signal and the second input signal and to generate a second output signal that is a shifted version of the second input signal.

Abstract: Packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.

Abstract: A light-emitting device and optical communication system based on the light-emitting device is disclosed. The light-emitting device is formed in a float-zone substrate. The light-emitting device includes on the substrate lower surface a reflective layer and on the upper surface spaced apart doped regions. The portion of the upper surface between the doped regions is textured and optionally covered with an antireflection coating to enhance light emission. The light-emitting device can operate as a laser or as a light-emitting diode, depending on the reflectivities of the antireflection coating and the reflective layer.

Abstract: A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.

Abstract: According to some embodiments, a circuit includes a ring oscillator delay stage. The delay stage may include a first transistor, a second transistor, and an active inductor. A gate of the first transistor may receive a first input signal, a gate of the second transistor may receive a second input signal, a source of the second transistor may be coupled to a source of the first transistor, and the active inductor may be coupled to a drain of the first transistor.

Abstract: According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.

Abstract: A CML XOR logic circuit is provided that includes a pair of pull-up transistors, a pair of current source transistors and a logic switch network coupled between the pull-up transistors and the current source transistors. The logic switch network including a plurality of transistors divided into a first branch, a second branch and a third branch. A tail current flows through the first branch, the second branch or the third branch based on at least two input signals to the plurality of transistors.

Abstract: In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted version of the first input signal. The apparatus further includes a second pair of transistors to receive the first input signal and the second input signal and to generate a second output signal that is a shifted version of the second input signal.

Abstract: According to some embodiments, a circuit includes a ring oscillator delay stage. The delay stage may include a first transistor, a second transistor, and an active inductor. A gate of the first transistor may receive a first input signal, a gate of the second transistor may receive a second input signal, a source of the second transistor may be coupled to a source of the first transistor, and the active inductor may be coupled to a drain of the first transistor.

Abstract: According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.

Abstract: An integrated circuit die includes optical interconnect ports on a first side and electrical interconnect ports on a second side.

Abstract: A clock and data recovery circuit is provided that includes a phase/frequency detector to receive input data and multiphase clock signals. The phase/frequency detector including a first set of flip-flop circuits each to sample the input data at one of the multiphase clock signals and each to output a sampled data, and a second set of flip-flop circuits to retime the sampled data based on a similar clock signal applied to each of the second set of flip-flop circuits.

Abstract: A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.

Abstract: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.

Abstract: A CML XOR logic circuit is provided that includes a pair of pull-up transistors, a pair of current source transistors and a logic switch network coupled between the pull-up transistors and the current source transistors. The logic switch network including a plurality of transistors divided into a first branch, a second branch and a third branch. A tail current flows through the first branch, the second branch or the third branch based on at least two input signals to the plurality of transistors.