Abstract: A new trans-impedance amplifier (TIA) with low noise is provided. The TIA may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, and a pair of capacitors electrically connected in series, which are electrically connected in parallel. The structure can lead to a reduced noise level of the TIA.

Abstract: A new trans-impedance amplifier (TIA) with low noise is provided. The TIA may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, and a pair of capacitors electrically connected in series, which are electrically connected in parallel. The structure can lead to a reduced noise level of the TIA.

Abstract: A trans-impedance amplifier (TIA) may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, a pair of capacitors electrically connected in series, a differential output node, a third PMOS transistor, and a fourth pair of NMOS transistors cross-coupled between the pair of output circuits of the output driving stage. The structure can lead to a reduced noise level and a reduced peak transient current level of the TIA.

Abstract: A Weil code generator and a method of generating Weil codes with a Weil code length (N) are provided. The Weil code generator includes a plurality of parallel channels (10), a multi-channel read arbiter (20), and two parallel Legendre ROMs (30), which are connected in series. A channel of the plurality of channels stores a current Weil code to demodulate signals from a satellite. The multi-channel read arbiter (20) may determine a win channel from the plurality of channels. The two Legendre ROMs (30) respectively store a first and a second Legendre sequences (LS1, LS2) each having a Legendre sequence length (2N) being double the Weil code length (N). The Weil code generator may generate Weil codes efficiently.

Abstract: A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

Abstract: An ADC circuit is provided. The ADC circuit may include an array of bit capacitors; a comparator electrically connected to the bit capacitors; a NOR gate electrically connected to the comparator; an AND gate to create an asynchronous clock (ACLK) based on a digital output from the NOR and a synchronous clock (CLKin); a delay control circuit to receive the asynchronous clock and to create a delayed asynchronous clock (ACLKd); and a SAR control circuit to receive a digital output from an output end of the comparator, to receive the delayed asynchronous clock, to transmit a bit control signal (B<9:1>) to the bit capacitors, and to transmit a delay control word (DL<7:1>) to the delay control circuit. The ADC circuit can create an asynchronous comparator clock (CKcmp) with a maximum delay value (Td_max), thus leading to an improved conversion linearity and a reduced power consumption.

Abstract: A power amplifier includes a digital-to-analog converter, a loop filter, a driver circuit, a first adjustable reference resistor and a second adjustable reference resistor. A circuit includes an overcurrent protection circuit and a power amplifier, wherein the overcurrent protection circuit is communicatively coupled to the power amplifier. The digital-to-analog converter is configured to receive a digital signal and to output an analog signal, the driver circuit communicatively coupled to the loop filter and at least one of a first output port and a second output port of the power amplifier.

Abstract: A power amplifier includes a digital-to-analog converter, a loop filter, a driver circuit, a first adjustable reference resistor and a second adjustable reference resistor. A circuit includes an overcurrent protection circuit and a power amplifier, wherein the overcurrent protection circuit is communicatively coupled to the power amplifier. The digital-to-analog converter is configured to receive a digital signal and to output an analog signal, the driver circuit communicatively coupled to the loop filter and at least one of a first output port and a second output port of the power amplifier.

Abstract: A radio-frequency (RF) power rectifier circuit is provided. The RF power rectifier circuit includes a pair of differential voltage input nodes, a pair of input transistors respectively connected to the pair of differential voltage input nodes, a current mirror including a first, a second, and a third transistors, a pair of cascode transistors electrically connected between the pair of input transistors and the first transistor, a control resistor and a control transistor, and an output node. The control resistor is electrically connected to a source of the control transistor and the ground to provide a DC bias to the control transistor, and the control transistor is electrically connected to the second transistor to provide a dynamic bias to the pair of cascode transistors. This structure can lead to an increased input voltage range and reduced power consumption.

Abstract: A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.

Abstract: A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

Abstract: A low pass filter embedded digital-to-analog converter including a first switch coupled to a first node that is coupled to a fourth switch and a first capacitor, a second switch coupled to a second node that is coupled to the first capacitor and a third switch, a negative input of a first operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor, and an output port of the first operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch.

Abstract: A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.

Abstract: A power amplifier includes an operational amplifier, a ramp generator communicatively coupled to both a first comparator and a second comparator; the first comparator further communicatively coupled to a negative output port of the operational amplifier; the second comparator further communicatively coupled to a positive output port of the operational amplifier; a first inverter communicatively coupled to the first comparator; a second inverter communicatively coupled to the second comparator; wherein the first inverter is communicatively coupled to both a positive input port of the operational amplifier via a first resistor and coupled to a negative input port of the operational amplifier via a fourth resistor; and the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor.

Abstract: A power amplifier includes an operational amplifier, a ramp generator communicatively coupled to both a first comparator and a second comparator; the first comparator further communicatively coupled to a negative output port of the operational amplifier; the second comparator further communicatively coupled to a positive output port of the operational amplifier; a first inverter communicatively coupled to the first comparator; a second inverter communicatively coupled to the second comparator; wherein the first inverter is communicatively coupled to both a positive input port of the operational amplifier via a first resistor and coupled to a negative input port of the operational amplifier via a fourth resistor; and the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor.

Abstract: A new demodulator with consistent sensibility to signals received from different directions, low power consumption, and low manufacturing cost is provided. The demodulator may include a first demodulator branch and a second demodulator branch electrically connected in parallel, and a DC circuit to provide DC power to the demodulator. The DC circuit has a first diode and a second diode electrically connected in series between a DC power supply Vcc and the ground. The second demodulator branch can share a low pass filter and a DC blocking capacitor of the first demodulator branch for example, and can multiplex or reuse a bias current from the first demodulator branch.

Abstract: A new demodulator with consistent sensibility to signals received from different directions, low power consumption, and low manufacturing cost is provided. The demodulator may include a first demodulator branch and a second demodulator branch electrically connected in parallel, and a DC circuit to provide DC power to the demodulator. The DC circuit has a first diode and a second diode electrically connected in series between a DC power supply Vcc and the ground. The second demodulator branch can share a low pass filter and a DC blocking capacitor of the first demodulator branch for example, and can multiplex or reuse a bias current from the first demodulator branch.

Abstract: A new demodulator with consistent sensibility to signals received from different directions and low power consumption is provided. The demodulator may include a first demodulator branch and a second demodulator branch electrically connected in parallel, and a DC circuit to provide DC power to the demodulator. The DC circuit has a first diode and a second diode electrically connected in series between a DC power supply Vcc and the ground. The second demodulator branch can multiplex or reuse a bias current from the first demodulator branch.

Abstract: A CMOS IR transceiver includes an IR transmitter circuit, an IR receiver circuit, and an IR diode configured to either emit or receive an IR signal. CMOS elements, such as a PMOS current mirror, a PMOS switch, a NMOS switch, a NMOS current mirror, and a receiver enabling PMOSFET switch are used in the CMOS IR transceiver. The CMOS IR transceiver may have advantages of increased integration, occupying less space, and lower cost.

Abstract: A method in an on-board unit comprising: receiving and decoding, with a transceiver, a broadcast packet (BCP) from a road side unit (RSU); processing BCP with a micro controller unit (MCU), wherein processing comprises determining whether there is a first interrupt from the transceiver, wherein the first interrupt is used to interrupt idle state of MCU; searching for low level state from a falling edge after the first interrupt; determining whether duration time of low level is within a time range; inputting one byte into the transceiver if duration time is within the range and clearing the first interrupt; determining whether there is a second interrupt from the transceiver, wherein the second interrupt is used to interrupt data reception; processing data in BCP if there is second interrupt; and converting, with the transceiver, processed data to a wireless signal and transmitting the signal to RSU.