Abstract: An ASK demodulator comprises a rectification circuit which receives and rectifies an ASK signal to generate a rectified current; an active load circuit is coupled to the rectification circuit and receives the rectified current and present an impedance which is inversely proportional to at least a part of the rectified current when a frequency of a base band signal meets a preset condition; a comparator is coupled to the rectification circuit and the active load circuit and receives a reference voltage and a voltage generated based on, at least in part, the rectified current and the impedance, and compares the reference voltage and the generated voltage to generate a demodulated signal.

Abstract: An ASK demodulator comprises a rectification circuit which receives and rectifies an ASK signal to generate a rectified current; an active load circuit is coupled to the rectification circuit and receives the rectified current and present an impedance which is inversely proportional to at least a part of the rectified current when a frequency of a base band signal meets a preset condition; a comparator is coupled to the rectification circuit and the active load circuit and receives a reference voltage and a voltage generated based on, at least in part, the rectified current and the impedance, and compares the reference voltage and the generated voltage to generate a demodulated signal.

Abstract: An ASK modulator includes a baseband unit which obtains a sequence comprising at least one amplitude value and adds an additional value to each of the at least one amplitude value to generate a modified sequence; a digital-to-analog converter coupled to the baseband unit, the digital-to-analog converter converts the modified sequence to generate a first signal, the additional value is determined based on a half scale of the digital-analog converter; and a mixer which receives the first signal and a second signal and generate a modulated signal by mixing the first signal with the second signal.

Abstract: A regulator includes an output circuit receives a feedback voltage and provides an output current based on the feedback voltage, an output voltage of the regulator is based on the output current; a first MOSFET coupled to the output circuit and receives the output voltage of the regulator; a second MOSFET coupled to the first MOSFET provides the feedback voltage based on, at least in part, the output voltage; a current sink coupled to the first MOSFET and the second MOSFET and receive jointly a current from the first MOSFET and a current from the second MOSFET; a current source coupled to the second MOSFET and provides the second MOSFET with the current, a connection of the current source and the second MOSFET is further coupled to the output circuit and provides the feedback voltage based on, at least in part, the current in the second MOSFET.

Abstract: A new demodulator with low power consumption and high gain which is suitable for CMOS integration is provided. The demodulator makes use of a MOS configured in a “common-source” status so as to achieve a desirable gain.

Abstract: A wake-up circuit, comprising: a control signal generation circuit comprising: a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency thereof; a first comparison circuit and a second comparison circuit both coupled to the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal; the frequency detector further comprises: an indication generation circuit configured to generate a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies.

Abstract: A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.

Abstract: A method comprises: disposing an on-board unit at a preset relative position with respect to a road-side unit; transmitting a signal by the road-side unit; receiving the signal by the on-board unit and detecting a strength of the received signal; calculating, by the on-board unit, a calculated strength of the received signal according to the detected strength of the received signal; storing the calculated strength of the received signal in a memory accessible by the on-board unit; using the stored calculated strength of the received signal to determine if payment of a toll should be made.

Abstract: A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.

Abstract: A new demodulator with low power consumption and high gain which is suitable for CMOS integration is provided. The demodulator makes use of a MOS configured in a “common-source” status so as to achieve a desirable gain.

Abstract: A wake-up circuit, comprising: a control signal generation circuit comprising: a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency thereof; a first comparison circuit and a second comparison circuit both coupled to the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal; the frequency detector further comprises: an indication generation circuit configured to generate a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies.