Patents by Inventor Jie Hao

Jie Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10522444
    Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
  • Patent number: 10496758
    Abstract: According to one embodiment, According to one embodiment, a machine translation apparatus includes a circuitry and a memory. The circuitry is configured to input a sentence of a first language, to segment the sentence to obtain a plurality of phrases, to search a translation model for translation options of a second language of each of the plurality of phrases, and to select top N translation options with high probabilities for decoding. N is an integer equal to or larger than 1. Furthermore, the circuitry is configured to combine the top N translation options of the plurality of phases to obtain a plurality of translation hypotheses, to search user history phrase pairs for the translation hypotheses, and to increase a score of a translation hypothesis existing in the user history phrase pairs. The memory is configured to store the score of the translation hypothesis.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Zhengshan Xue, Dakun Zhang, Jichong Guo, Jie Hao
  • Patent number: 10446073
    Abstract: A driving method for a display panel is provided, including the following steps: providing a first control signal, and providing a second control signal, where a voltage change of the second control signal compensates for a voltage change of the first control signal.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 15, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chun-Kuei Wen, Chun-Yu Chen, Yi-Hao Wang, Jie-Chuan Huang, Hung-Min Shih
  • Publication number: 20190305107
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Kuo-Ju CHEN, Su-Hao LIU, Chun-Hao KUNG, Liang-Yin CHEN, Huicheng CHANG, Kei-Wei CHEN, Hui-Chi HUANG, Kao-Feng LIAO, Chih-Hung CHEN, Jie-Huang HUANG, Lun-Kuang TAN, Wei-Ming YOU
  • Publication number: 20190297633
    Abstract: Methods, systems, computer-readable media, and apparatuses for to managing use of a satellite positions system (SPS) receiver in conjunction with one or more radio access technology (RAT) transmitters. In certain embodiments, a controller can be used to prioritize reception by the SPS receiver over transmission by the one or more RAT transmitters.
    Type: Application
    Filed: June 12, 2019
    Publication date: September 26, 2019
    Inventors: Jie Wu, Chun-Hao Hsu, Liang Zhao, Parvathanathan Subrahmanya, Amit Mahajan, Nitin Pant, Vieri Vanghi
  • Publication number: 20190286268
    Abstract: A touch display panel includes a pixel array, a touch module, and a multiplexer circuit. The pixel array includes a plurality of pixels, a plurality of gate lines, and a plurality of source lines. The pixels are electrically coupled to the source lines and the gate lines. The touch module and the pixel array are overlapped. The multiplexer circuit is coupled between all of the source lines and a source driver and has a plurality of multiplexers. The multiplexers are respectively coupled to n source lines and respectively include a plurality of switches and a bypass trace. The switches are respectively coupled between the first source line to the (n?1)th source line of the n source lines and the source drivers. The bypass trace is coupled between the nth source line of the n source lines and the source driver.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 19, 2019
    Applicant: Au Optronics Corporation
    Inventors: Rong-Fu Lin, Chun-Wei Chang, Shu-Hao Huang, Sung-Yu Su, Jie-Chuan Huang, Yun-I Liu
  • Patent number: 10412752
    Abstract: Methods, systems, computer-readable media, and apparatuses for to managing use of a satellite positions system (SPS) receiver in conjunction with one or more radio access technology (RAT) transmitters. In certain embodiments, a controller can be used to prioritize reception by the SPS receiver over transmission by the one or more RAT transmitters.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jie Wu, Chun-Hao Hsu, Liang Zhao, Parvathanathan Subrahmanya, Amit Mahajan, Nitin Pant, Vieri Vanghi
  • Publication number: 20190213137
    Abstract: The present invention provides a method for managing a flash memory module, wherein the method comprises: reading a logical address to physical address (L2P) mapping table from the flash memory module; compressing the L2P mapping table to generate a compressed mapping table, wherein the compressed mapping table records a reference physical address and whether a corresponding physical address of each logical address is the reference physical address plus an offset value; and when receiving a read command asking for reading data corresponding to a specific logical address, referring to the compressed mapping table to determine a specific physical address corresponding to the specific logical address, and reading the data from the flash memory module according to the specific physical address.
    Type: Application
    Filed: June 29, 2018
    Publication date: July 11, 2019
    Inventors: Chien-Cheng Lin, Chia-Chi Liang, Jie-Hao Lee
  • Publication number: 20190171559
    Abstract: The present invention provides a method for accessing a flash module, wherein the method includes: creating a logical address group table corresponding to a block of the flash module, wherein the logical address group table records states of a plurality of logical address groups, and the state of each logical address group represents if data written into the block has any logical address within the logical address group; when the block is under a garbage collection operation, referring to the logical address group table to read at least one logical address to physical address (L2P) mapping table; and determining valid pages and invalid pages within the block according to the L2P table, for performing the garbage collection operation.
    Type: Application
    Filed: June 18, 2018
    Publication date: June 6, 2019
    Inventors: Jie-Hao Lee, Hsuan-Ping Lin
  • Publication number: 20190157148
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.
    Type: Application
    Filed: June 28, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Po HSIEH, Su-Hao LIU, Hong-Chih LIU, Jing-Huei HUANG, Jie-Huang HUANG, Lun-Kuang TAN, Huicheng CHANG, Liang-Yin CHEN, Kuo-Ju CHEN
  • Publication number: 20190108131
    Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing at least one checking operation to obtain at least one checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device, wherein the L2P table includes address mapping information for accessing the target data, and performing the at least one checking operation to obtain at least one checking result includes checking whether a first L2P-table index pointing toward the L2P table and a second L2P-table index sent from the host device are equivalent to each other; and reading the target data from the NV memory, and sending the target data to the host device.
    Type: Application
    Filed: January 2, 2018
    Publication date: April 11, 2019
    Inventors: Jie-Hao Lee, Cheng-Yu Yu
  • Publication number: 20190107964
    Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing a checking operation to obtain a checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device; reading the target data and associated metadata from the NV memory, wherein a latest version of the L2P table is available in the RAM when reading the target data from the NV memory is performed; and checking whether a recorded logical address within the metadata and the logical address received from the host device are equivalent to each other, to control whether to send the target data to the host device.
    Type: Application
    Filed: January 1, 2018
    Publication date: April 11, 2019
    Inventors: Chia-Chi Liang, Jie-Hao Lee
  • Publication number: 20190065394
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes: building a physical address to logical address (P2L) table; receiving a read command asking for a data within the flash memory module, wherein the read command includes a first logical address; if the P2L table does not include information associated with the first logical address, reading a logical address to physical address (L2P) table from the flash memory module, and searching a first physical address corresponding to the first logical address according to the L2P table, wherein the first physical address is used to read the data from the flash memory module; and using the P2L table to update the L2P table.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 28, 2019
    Inventors: Jie-Hao Lee, Chun-Ju Chen
  • Patent number: 10168913
    Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 1, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Cheng Lin, Jie-Hao Lee
  • Patent number: 10109272
    Abstract: According to one embodiment, an apparatus for training a neural network acoustic model includes a calculating unit, a clustering unit, and a sharing unit. The calculating unit calculates, based on training data including a training speech and a labeled phoneme state, scores of phoneme states different from the labeled phoneme state. The clustering unit clusters a phoneme state whose score is larger than a predetermined threshold and the labeled phoneme state. The sharing unit shares probability of the labeled phoneme state by the clustered phoneme states. The training unit trains the neural network acoustic model based on the training speech and the clustered phoneme states.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Huifeng Zhu, Yan Deng, Pei Ding, Kun Yong, Jie Hao
  • Patent number: 10061768
    Abstract: According to one aspect, there is provided an apparatus for improving a bilingual corpus including a plurality of sentence pairs of a first language and a second language and word alignment information of each of the sentence pairs, the apparatus comprises: an extracting unit for extracting a split candidate from word alignment information of a given sentence pair; a calculating unit for calculating split confidence of said split candidate; a comparing unit for comparing said split confidence and a pre-set threshold; and a splitting unit for splitting said given sentence pair at said split candidate in a case that said split confidence is larger than said pre-set threshold.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 28, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tao Su, Dakun Zhang, Jie Hao
  • Publication number: 20180207195
    Abstract: An oxidized ?-1,4-oligoglucuronic acid, and a preparation method therefor and uses thereof. By using abundant starch, especially soluble starch, in the natural world as the raw material, all 6-site hydroxyl groups of the starch ?-1,4-polyglucose are oxidized into carboxyl groups to form glucuronic acid under the action of a sodium bromide (NaBr)-2,2,6,6-tetramethyl piperidine oxide (TEMPO)-sodium hypochlorite (NaClO) oxidation system, and the oxidized oligoglucuronic acid having an open ring at an end is prepared by controlling reaction conditions. The compound has obvious anti-cerebral ischemia activity, and can be developed into a potential anti-cerebral ischemia drug.
    Type: Application
    Filed: May 20, 2016
    Publication date: July 26, 2018
    Applicant: SHANGHAI GREEN VALLEY PHARMACEUTICAL CO., LTD.
    Inventors: Zhenqing ZHANG, Jie HAO, Shichang SUN, Huiling ZHANG
  • Publication number: 20180207194
    Abstract: An oxidized ?-1,4-oligoglucuronic acid, and a preparation method therefor and uses thereof. By using abundant cellulose in the natural world as the raw material, all 6-site hydroxyl groups of the cellulose ?-1,4-polyglucose is oxidized into carboxyl groups to form glucuronic acid under the action of a sodium bromide (NaBr)-2,2,6,6-tetramethyl piperidine oxide (TEMPO)-sodium hypochlorite (NaClO) oxidation system, and the oxidized oligoglucuronic acid having an open ring at an end is prepared by controlling reaction conditions. The compound has obvious anti-cerebral ischemia activity, and can be developed into a potential anti-cerebral ischemia drug.
    Type: Application
    Filed: May 20, 2016
    Publication date: July 26, 2018
    Applicant: SHANGHAI GREEN VALLEY PHARMACEUTICAL CO., LTD.
    Inventors: Zhenqing ZHANG, Jie HAO, Shichang SUN, Huiling ZHANG
  • Patent number: 10013210
    Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller equally distributes the TLC-data blocks into three regions. In a first stage, the controller determines a first TLC-data block corresponding to the logic address of a prewrite data sector, defines the region that contains the first TLC-data block as a first region, and determines whether the first TLC-data block has valid data. When the first TLC-data block does not have valid data, the controller selects a second TLC-data block and a third TLC-data block from the regions other than the first region for writing the prewrite data sector, into the first TLC-data block, the second TLC-data block and the third TLC-data block by a SLC storage mode.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 3, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Cheng Lin, Jie-Hao Lee
  • Patent number: D876341
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 25, 2020
    Assignee: NIO CO., LTD.
    Inventors: Kris Tomasson, Juho Suh, Jim Baste, Lijian Xia, Chao Yang, Zhiling Zhao, Robert James Orr, IV, Jie Shao, Tianlei Hao, Wenjie Hou, Patrick Niall McGoldrick, Christoph Proessler, Matthew Garwood, Michael Tropper