Abstract: According to one embodiment, an apparatus trains a neural network language model. The apparatus includes a calculating unit and a training unit. The calculating unit calculates probabilities of n-gram entries based on a training corpus. The training unit trains the neural network language model based on the n-gram entries and the probabilities of the n-gram entries.

Abstract: According to one embodiment, an apparatus trains a neural network auxiliary model used to calculate a normalization factor of a neural network language model. The apparatus includes a calculating unit and a training unit. The calculating unit calculates a vector of at least one hidden layer and a normalization factor by using the neural network language model and a training corpus. The training unit trains the neural network auxiliary model by using the vector of the at least one hidden layer and the normalization factor as an input and an output respectively.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

Abstract: The data storage device included a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages, and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory. The microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory to record mapping information between the host and the flash memory and records a link table indicator on the flash memory to indicate a position of the link table. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. Further, the microcontroller erases user of logical addresses corresponding to N logical-to-physical address mapping tables.

Abstract: According to one embodiment, an apparatus for training a neural network acoustic model includes a calculating unit, a clustering unit, and a sharing unit. The calculating unit calculates, based on training data including a training speech and a labeled phoneme state, scores of phoneme states different from the labeled phoneme state. The clustering unit clusters a phoneme state whose score is larger than a predetermined threshold and the labeled phoneme state. he sharing unit shares probability of the labeled phoneme state by the clustered phoneme states. The training unit trains the neural network acoustic model based on the training speech and the clustered phoneme states.

Abstract: The data storage device included a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages, and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory. The microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory to record mapping information between the host and the flash memory and records a link table indicator on the flash memory to indicate a position of the link table. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. Further, the microcontroller erases user of logical addresses corresponding to N logical-to-physical address mapping tables.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller distributes TLC-data blocks of the flash memory into three regions, obtains three sub-prewrite data sectors according to a prewrite data sector and a logic address, determines a first TLC-data block according to the logic address, selects a new first TLC-data block with the lowest erase count from the first region when the first TLC-data block has valid data, selects two TLC-data blocks according to the new first TLC-data block, writes the three sub-prewrite data sectors into the new first TLC-data block and the two selected TLC-data blocks, and maps the first new TLC-data block and the two selected TLC-data blocks to the logic address.

Abstract: A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block.

Abstract: A data storage device and a flash memory control method with high erasing efficiency are disclosed. A microcontroller is configured to maintain a plurality of logical-to-physical address mapping tables and a link table on a flash memory to record mapping information between a host and the flash memory. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. When erasing user data of logical addresses corresponding to N logical-to-physical address mapping tables, the microcontroller is configured to invalidate N entries corresponding to the N logical-to-physical address mapping tables in the link table, where N is an integer.

Abstract: A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MU:s) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access mernoiy to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block.

Abstract: A data storage device and a flash memory control method with a power recovery design. A microcontroller is configured to allocate a flash memory to provide a first block from the blocks to work as a run-time write block for reception of write data. During a power recovery process due to an unexpected power-off event that interrupted write operations on the first block, the microcontroller is configured to allocate the flash memory to provide a second block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block.

Abstract: A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block.

Abstract: A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to establish a first physical-to-logical address mapping table (F2H table) in a random access memory (RAM) for a first run-time write block containing MLCs. The microcontroller is further configured to establish a second F2H table in the RAM for a second run-time write block containing SLCs. When data that was previously stored in the first run-time write block with un-uploaded mapping information in the first F2H table is updated into the second run-time write block, the microcontroller is configured to update a logical-to-physical address mapping table (H2F table) in accordance with the first F2H table. The H2F table is provided within the flash memory.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller equally distributes the TLC-data blocks into three regions. In a first stage, the controller determines a first TLC-data block corresponding to the logic address of a prewrite data sector, defines the region that contains the first TLC-data block as a first region, and determines whether the first TLC-data block has valid data. When the first TLC-data block does not have valid data, the controller selects a second TLC-data block and a third TLC-data block from the regions other than the first region for writing the prewrite data sector, into the first TLC-data block, the second TLC-data block and the third TLC-data block by a SLC storage mode.

Abstract: A data storage device with flash memory and a flash memory control method are disclosed, which upload the physical-to-logical address mapping information of one block to the flash memory section by section. A microcontroller is configured to allocate a flash memory to provide a first run-time write block. Between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with just part of a first physical-to-logical address mapping table. The logical-to-physical address mapping table is provided within the flash memory. The first physical-to-logical address mapping table is established in the random access memory to record logical addresses corresponding to physical addresses of one block.

Abstract: According to one embodiment, an apparatus for extracting keywords from a single document includes a key sentence extraction unit and a keyword extraction unit. The key sentence extraction unit extracts key sentences from the single document. The keyword extraction unit extracts keywords from the key sentences.

Abstract: According to one embodiment, an apparatus for improving a language model of a speech recognition system includes an extracting unit, a classifying unit, and a setting unit. The extracting unit extracts user words from a user document provided by a user. The classifying unit classifies the user words based on a system lexicon of the speech recognition system. The setting unit sets weighting factor of a probability of the language model for at least one of the user words based on the classified result.

Abstract: According to one embodiment, an apparatus for improving a neural network language model of a speech recognition system includes a word classifying unit, a language model training unit and a vector incorporating unit. The word classifying unit classifies words in a lexicon of the speech recognition system. The language model training unit trains a class-based language model based on the classified result. The vector incorporating unit incorporates an output vector of the class-based language model into a position index vector of the neural network language model and use the incorporated vector as an input vector of the neural network language model.

Abstract: A data storage device and a flash memory control method with high efficiency are disclosed. The random access memory of the data storage device is allocated to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table. When recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller of the data storage device is configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area.

Abstract: A data access method and device for parallel FFT computation. In the method, FFT data and twiddle factors are stored in multi-granularity parallel memories, and divided into groups throughout the computation flow according to a uniform butterfly representation. Each group of data involves multiple butterflies that support parallel computation. Meanwhile, according to the butterfly representation, it is convenient to generate data address and twiddle factor coefficient address for each group. With different R/W granularities, it is possible to read/write data and corresponding twiddle factors in parallel from the multi-granularity memories. The method and device further provide data access devices for parallel FFT computation. In the method and device, no conflict will occur during read/write operations of memories, and no extract step is required for sorting the read/written data. Further, the method and device can flexibly define the parallel granularity according to particular applications.