Patents by Inventor Jie Hao

Jie Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10898509
    Abstract: An oxidized ?-1,4-oligoglucuronic acid, and a preparation method therefor and uses thereof. By using abundant starch, especially soluble starch, in the natural world as the raw material, all 6-site hydroxyl groups of the starch ?-1,4-polyglucose are oxidized into carboxyl groups to form glucuronic acid under the action of a sodium bromide (NaBr)-2,2,6,6-tetramethyl piperidine oxide (TEMPO)-sodium hypochlorite (NaClO) oxidation system, and the oxidized oligoglucuronic acid having an open ring at an end is prepared by controlling reaction conditions. The compound has obvious anti-cerebral ischemia activity, and can be developed into a potential anti-cerebral ischemia drug.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 26, 2021
    Assignee: SHANGHAI GREEN VALLEY PHARMACEUTICAL CO., LTD.
    Inventors: Zhenqing Zhang, Jie Hao, Shichang Sun, Huiling Zhang
  • Publication number: 20200412379
    Abstract: Uncorrectable (UNC) marking on a non-volatile memory is provided. In response to a UNC marking command issued by a host, a cyclic redundancy check (CRC) engine provides a specific CRC code to mark a logical address segment as uncorrectable, wherein the logical address segment is requested to be marked as uncorrectable by the UNC marking command. As long as the specific CRC code is recognized, a CRC procedure is not required and the data requested by the host is directly determined as uncorrectable.
    Type: Application
    Filed: February 10, 2020
    Publication date: December 31, 2020
    Inventors: Hsuan-Ping LIN, Jie-Hao LEE
  • Publication number: 20200409835
    Abstract: An efficient control technology for non-volatile memory is shown. A non-volatile memory provides a storage space that is divided into blocks. When programming the write data issued by the host to the non-volatile memory, the programming order of the blocks is recorded. Garbage collection is based on the recorded programming order. Sequential data can be collected to the destination block in sequence.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 31, 2020
    Inventors: Jie-Hao LEE, Yi-Kang CHANG, Hsuan-Ping LIN
  • Publication number: 20200374005
    Abstract: An indoor visible light positioning method and system based on a single LED lamp. The system includes an LED communication module and a smartphone module. The LED communication module sends its coordinates and shape data to the smartphone module. The smartphone module includes an inertial measurement unit (IMU) and a camera. The IMU is configured to obtain movement data of a smartphone. The camera is configured to shoot video streams of the LED lamp. Computing processing is performed on center point coordinates of the LED lamp and IMU data in the video streams, and constraints are provided by using a homography matrix of ellipses in the video streams, to obtain accurate location information of the smartphone, and provide location-based services such as navigation and query for a user.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 26, 2020
    Inventors: Jie HAO, Jing CHEN
  • Patent number: 10698809
    Abstract: The present invention provides a method for accessing a flash module, wherein the method includes: creating a logical address group table corresponding to a block of the flash module, wherein the logical address group table records states of a plurality of logical address groups, and the state of each logical address group represents if data written into the block has any logical address within the logical address group; when the block is under a garbage collection operation, referring to the logical address group table to read at least one logical address to physical address (L2P) mapping table; and determining valid pages and invalid pages within the block according to the L2P table, for performing the garbage collection operation.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Hsuan-Ping Lin
  • Patent number: 10606761
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes: building a physical address to logical address (P2L) table; receiving a read command asking for a data within the flash memory module, wherein the read command includes a first logical address; if the P2L table does not include information associated with the first logical address, reading a logical address to physical address (L2P) table from the flash memory module, and searching a first physical address corresponding to the first logical address according to the L2P table, wherein the first physical address is used to read the data from the flash memory module; and using the P2L table to update the L2P table.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 31, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Chun-Ju Chen
  • Patent number: 10496758
    Abstract: According to one embodiment, According to one embodiment, a machine translation apparatus includes a circuitry and a memory. The circuitry is configured to input a sentence of a first language, to segment the sentence to obtain a plurality of phrases, to search a translation model for translation options of a second language of each of the plurality of phrases, and to select top N translation options with high probabilities for decoding. N is an integer equal to or larger than 1. Furthermore, the circuitry is configured to combine the top N translation options of the plurality of phases to obtain a plurality of translation hypotheses, to search user history phrase pairs for the translation hypotheses, and to increase a score of a translation hypothesis existing in the user history phrase pairs. The memory is configured to store the score of the translation hypothesis.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Zhengshan Xue, Dakun Zhang, Jichong Guo, Jie Hao
  • Publication number: 20190213137
    Abstract: The present invention provides a method for managing a flash memory module, wherein the method comprises: reading a logical address to physical address (L2P) mapping table from the flash memory module; compressing the L2P mapping table to generate a compressed mapping table, wherein the compressed mapping table records a reference physical address and whether a corresponding physical address of each logical address is the reference physical address plus an offset value; and when receiving a read command asking for reading data corresponding to a specific logical address, referring to the compressed mapping table to determine a specific physical address corresponding to the specific logical address, and reading the data from the flash memory module according to the specific physical address.
    Type: Application
    Filed: June 29, 2018
    Publication date: July 11, 2019
    Inventors: Chien-Cheng Lin, Chia-Chi Liang, Jie-Hao Lee
  • Publication number: 20190171559
    Abstract: The present invention provides a method for accessing a flash module, wherein the method includes: creating a logical address group table corresponding to a block of the flash module, wherein the logical address group table records states of a plurality of logical address groups, and the state of each logical address group represents if data written into the block has any logical address within the logical address group; when the block is under a garbage collection operation, referring to the logical address group table to read at least one logical address to physical address (L2P) mapping table; and determining valid pages and invalid pages within the block according to the L2P table, for performing the garbage collection operation.
    Type: Application
    Filed: June 18, 2018
    Publication date: June 6, 2019
    Inventors: Jie-Hao Lee, Hsuan-Ping Lin
  • Publication number: 20190107964
    Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing a checking operation to obtain a checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device; reading the target data and associated metadata from the NV memory, wherein a latest version of the L2P table is available in the RAM when reading the target data from the NV memory is performed; and checking whether a recorded logical address within the metadata and the logical address received from the host device are equivalent to each other, to control whether to send the target data to the host device.
    Type: Application
    Filed: January 1, 2018
    Publication date: April 11, 2019
    Inventors: Chia-Chi Liang, Jie-Hao Lee
  • Publication number: 20190108131
    Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing at least one checking operation to obtain at least one checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device, wherein the L2P table includes address mapping information for accessing the target data, and performing the at least one checking operation to obtain at least one checking result includes checking whether a first L2P-table index pointing toward the L2P table and a second L2P-table index sent from the host device are equivalent to each other; and reading the target data from the NV memory, and sending the target data to the host device.
    Type: Application
    Filed: January 2, 2018
    Publication date: April 11, 2019
    Inventors: Jie-Hao Lee, Cheng-Yu Yu
  • Publication number: 20190065394
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes: building a physical address to logical address (P2L) table; receiving a read command asking for a data within the flash memory module, wherein the read command includes a first logical address; if the P2L table does not include information associated with the first logical address, reading a logical address to physical address (L2P) table from the flash memory module, and searching a first physical address corresponding to the first logical address according to the L2P table, wherein the first physical address is used to read the data from the flash memory module; and using the P2L table to update the L2P table.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 28, 2019
    Inventors: Jie-Hao Lee, Chun-Ju Chen
  • Patent number: 10168913
    Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 1, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Cheng Lin, Jie-Hao Lee
  • Patent number: 10109272
    Abstract: According to one embodiment, an apparatus for training a neural network acoustic model includes a calculating unit, a clustering unit, and a sharing unit. The calculating unit calculates, based on training data including a training speech and a labeled phoneme state, scores of phoneme states different from the labeled phoneme state. The clustering unit clusters a phoneme state whose score is larger than a predetermined threshold and the labeled phoneme state. The sharing unit shares probability of the labeled phoneme state by the clustered phoneme states. The training unit trains the neural network acoustic model based on the training speech and the clustered phoneme states.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Huifeng Zhu, Yan Deng, Pei Ding, Kun Yong, Jie Hao
  • Patent number: 10061768
    Abstract: According to one aspect, there is provided an apparatus for improving a bilingual corpus including a plurality of sentence pairs of a first language and a second language and word alignment information of each of the sentence pairs, the apparatus comprises: an extracting unit for extracting a split candidate from word alignment information of a given sentence pair; a calculating unit for calculating split confidence of said split candidate; a comparing unit for comparing said split confidence and a pre-set threshold; and a splitting unit for splitting said given sentence pair at said split candidate in a case that said split confidence is larger than said pre-set threshold.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 28, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tao Su, Dakun Zhang, Jie Hao
  • Publication number: 20180207195
    Abstract: An oxidized ?-1,4-oligoglucuronic acid, and a preparation method therefor and uses thereof. By using abundant starch, especially soluble starch, in the natural world as the raw material, all 6-site hydroxyl groups of the starch ?-1,4-polyglucose are oxidized into carboxyl groups to form glucuronic acid under the action of a sodium bromide (NaBr)-2,2,6,6-tetramethyl piperidine oxide (TEMPO)-sodium hypochlorite (NaClO) oxidation system, and the oxidized oligoglucuronic acid having an open ring at an end is prepared by controlling reaction conditions. The compound has obvious anti-cerebral ischemia activity, and can be developed into a potential anti-cerebral ischemia drug.
    Type: Application
    Filed: May 20, 2016
    Publication date: July 26, 2018
    Applicant: SHANGHAI GREEN VALLEY PHARMACEUTICAL CO., LTD.
    Inventors: Zhenqing ZHANG, Jie HAO, Shichang SUN, Huiling ZHANG
  • Publication number: 20180207194
    Abstract: An oxidized ?-1,4-oligoglucuronic acid, and a preparation method therefor and uses thereof. By using abundant cellulose in the natural world as the raw material, all 6-site hydroxyl groups of the cellulose ?-1,4-polyglucose is oxidized into carboxyl groups to form glucuronic acid under the action of a sodium bromide (NaBr)-2,2,6,6-tetramethyl piperidine oxide (TEMPO)-sodium hypochlorite (NaClO) oxidation system, and the oxidized oligoglucuronic acid having an open ring at an end is prepared by controlling reaction conditions. The compound has obvious anti-cerebral ischemia activity, and can be developed into a potential anti-cerebral ischemia drug.
    Type: Application
    Filed: May 20, 2016
    Publication date: July 26, 2018
    Applicant: SHANGHAI GREEN VALLEY PHARMACEUTICAL CO., LTD.
    Inventors: Zhenqing ZHANG, Jie HAO, Shichang SUN, Huiling ZHANG
  • Patent number: 10013210
    Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller equally distributes the TLC-data blocks into three regions. In a first stage, the controller determines a first TLC-data block corresponding to the logic address of a prewrite data sector, defines the region that contains the first TLC-data block as a first region, and determines whether the first TLC-data block has valid data. When the first TLC-data block does not have valid data, the controller selects a second TLC-data block and a third TLC-data block from the regions other than the first region for writing the prewrite data sector, into the first TLC-data block, the second TLC-data block and the third TLC-data block by a SLC storage mode.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 3, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Cheng Lin, Jie-Hao Lee
  • Patent number: 9940058
    Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller distributes TLC-data blocks of the flash memory into three regions, obtains three sub-prewrite data sectors according to a prewrite data sector and a logic address, determines a first TLC-data block according to the logic address, selects a new first TLC-data block with the lowest erase count from the first region when the first TLC-data block has valid data, selects two TLC-data blocks according to the new first TLC-data block, writes the three sub-prewrite data sectors into the new first TLC-data block and the two selected TLC-data blocks, and maps the first new TLC-data block and the two selected TLC-data blocks to the logic address.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: April 10, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Cheng Lin, Jie-Hao Lee
  • Publication number: 20180075022
    Abstract: According to one embodiment, According to one embodiment, a machine translation apparatus includes a circuitry and a memory. The circuitry is configured to input a sentence of a first language, to segment the sentence to obtain a plurality of phrases, to search a translation model for translation options of a second language of each of the plurality of phrases, and to select top N translation options with high probabilities for decoding. N is an integer equal to or larger than 1. Furthermore, the circuitry is configured to combine the top N translation options of the plurality of phases to obtain a plurality of translation hypotheses, to search user history phrase pairs for the translation hypotheses, and to increase a score of a translation hypothesis existing in the user history phrase pairs. The memory is configured to store the score of the translation hypothesis.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 15, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Zhengshan XUE, Dakun ZHANG, Jichong GUO, Jie HAO