Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: Context information of a handshake between a source entity and a target entity is obtained at a security proxy. The context information is transmitted from the security proxy to a key manager. The key manager maintains a first private key of the security proxy. A first handshake message is received from the key manager. The first handshake message is generated at least based on the context information and signed with the first private key. The first handshake message is then transmitted to the target entity.

Abstract: A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated with backlight illumination from a direct-lit backlight unit. The backlight unit may include an array of light-emitting diodes (LEDs) on a printed circuit board. The display may have a notch to accommodate an input-output component. Reflective layers may be included in the notch. The backlight may include a color conversion layer with a property that varies as a function of position. The light-emitting diodes may be covered by a slab of encapsulant with recesses in an upper surface.

Abstract: A light-emitting element includes a pair of electrodes, a first light-emitting unit, a second light-emitting unit, and a charge generation layer. The first light-emitting unit, between the pair of electrodes, and the first light-emitting unit, includes a first light-emitting layer. The second light-emitting unit, between the pair of electrodes, includes a second light-emitting layer. A first luminescent layer includes a first main body material, a second main body material, a first guest material, and a first auxiliary material, and the first main body material forms a first excimer complex with the second main body material. A first excited triplet state energy level of the first auxiliary material is lower than a first excited triplet state energy level of the first excimer complex, and the first excited triplet state energy level of the first auxiliary material is higher than that of the first guest material.

Abstract: This invention relates to the fields of mRNA vaccines, mRNA therapy, and gene therapy and specifically to the use of gene expression vectors or PCR amplicons containing various 5?UTR sequences followed by coding sequences for in vitro and in vivo production of mRNA or proteins of interest.

Abstract: Compounds having formula (I), and enantiomers, and diastereomers, stereoisomers, pharmaceutically-acceptable salts thereof, are useful as kinase modulators, including RIPK1 modulation. All the variables are as defined herein.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a first gate line, a second gate line, and a first auxiliary gate portion. The semiconductor substrate comprises a semiconductor fin. The semiconductor fin extends substantially along a first direction. The first gate line and the second gate line extend substantially along a second direction different form the first direction from a top view. The first auxiliary gate portion connects the first gate line to the second gate line from the top view.

Abstract: Systems, methods, apparatuses, and computer program products for machine learning based channel state information (CSI) estimation and feedback configuration are provided. A method may include learning channel state information feedback from one or more user equipment as time series data. The method may also include building a predictive model for user equipment feedback based on the learned channel state information feedback. The method may further include configuring a channel state information trigger with the one or more user equipment based on the predictive model. In addition, the method may include signaling predicted channel state information to the one or more user equipment.

Abstract: A method, a computer program product, and a system for implementing a dynamic virtual database honeypot. The method includes relaying a query request received from a database client to a database and receiving, from the database, a response relating to the query request. The method also includes determining the query request is an attack on the database based on session information relating to the database and the database client, generating a honey token based on information contained within the response, generating an alternate response formatted in a same format as the response and containing artificial information that masks the information contained within the response. The method further includes inserting the honey token into the alternate response and transmitting the alternate response to the database client.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first and second diode in a semiconductor wafer, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer. The first diode is coupled between an input output (IO) pad and a first node. The second diode is coupled to the first diode, and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled to the first and second node, and between the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a reference voltage supply. The second diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit. The first conductive structure is configured to provide a reference voltage to the first signal tap region.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

Abstract: A power supply device is provided. The power supply device includes a power converter and a controller. The controller controls the power converter to generate an output power. The controller includes a first detection circuit and a second detection circuit. The first detection circuit detects the output power to obtain a first detection result. The first detection result is a variation of an output current value of the output power. The second detection circuit detects electrical characteristics other than the output current value to obtain a second detection result. The controller determines whether to limit output of the output power according to a relationship between the first detection result and the second detection result.

Abstract: A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.