Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: The present disclosure describes optical and optoelectronic assemblies that, in some cases, include screen-printed micro-spacers, as well as methods for manufacturing such assemblies and modules. For example, an optoelectronic device mounted on a substrate can include an optical sub-assembly including a first optical element and a first micro-spacer on the optical element. The optical sub-assembly can be disposed over the optoelectronic device, with a first air or vacuum gap separating the first optical element from the optoelectronic device, and the first micro-spacer laterally surrounding the first air or vacuum gap.

Abstract: A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.

Abstract: A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.

Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.

Abstract: The present disclosure describes optical and optoelectronic assemblies that, in some cases, include screen-printed micro-spacers, as well as methods for manufacturing such assemblies and modules. For example, an optoelectronic device mounted on a substrate can include an optical sub-assembly including a first optical element and a first micro-spacer on the optical element. The optical sub-assembly can be disposed over the optoelectronic device, with a first air or vacuum gap separating the first optical element from the optoelectronic device, and the first micro-spacer laterally surrounding the first air or vacuum gap.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: The present disclosure describes optical and optoelectronic assemblies that, in some cases, include screen-printed micro-spacers, as well as methods for manufacturing such assemblies and modules. For example, micro-spacers can be applied on a first optical element layer, and a second optical element layer can be provided on the first micro-spacers. By providing the second optical element layer on the first micro-spacers, the second optical element layer and the first optical element layer can be separated from one another by air or vacuum gaps each of which is laterally surrounded by a portion of the first micro-spacers.

Abstract: The present disclosure describes wafer-level processes for fabricating optoelectronic device subassemblies that can be mounted, for example, to a circuit substrate, such as a flexible cable or printed circuit board, and integrated into optoelectronic modules that include one or more optical subassemblies stacked over the optoelectronic device subassembly. The optoelectronic device subassembly can be mounted onto the circuit substrate using solder reflow technology even if the optical subassemblies are composed of materials that are not reflow compatible.

Abstract: A lithography system is provided. The lithography system includes a mask and an optical module. The optical module is configured to optically form an invisible pellicle over the mask to protect the mask from contaminant particles. As a solid pellicle used in the prior arts is omitted, the critical dimension (CD) error from the boarder effect due to reflection of some light by the solid pellicle and the exposure radiation energy consumption caused by the solid pellicle can be avoided.

Abstract: A method includes receiving a first target pattern of an integrated circuit (IC) that includes two first target features and two second target features. The method further includes deriving a second target pattern based on the first target pattern and a directed self-assembly (DSA) process, wherein the first target pattern is to be produced by a process that includes performing the DSA process with a guide pattern derived from the second target pattern. The second target pattern includes a third feature and a fourth feature. The third feature is designed for producing the two first target features with the DSA process, and the fourth feature is designed for producing the two second target features with the DSA process. The method further includes inserting one or more sub-DSA-resolution assistant features (SDRAF) into the second target pattern, the one or more SDRAF connecting the third and fourth features.

Abstract: The present disclosure describes wafer-level processes for fabricating optoelectronic device subassemblies that can be mounted, for example, to a circuit substrate, such as a flexible cable or printed circuit board, and integrated into optoelectronic modules that include one or more optical subassemblies stacked over the optoelectronic device subassembly. The optoelectronic device subassembly can be mounted onto the circuit substrate using solder reflow technology even if the optical subassemblies are composed of materials that are not reflow compatible.

Abstract: A lithography system is provided. The lithography system includes a mask and an optical module. The optical module is configured to optically form an invisible pellicle over the mask to protect the mask from contaminant particles.

Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.

Abstract: The present disclosure describes wafer-level processes for fabricating optoelectronic device subassemblies that can be mounted, for example, to a circuit substrate, such as a flexible cable or printed circuit board, and integrated into optoelectronic modules that include one or more optical subassemblies stacked over the optoelectronic device subassembly. The optoelectronic device subassembly can be mounted onto the circuit substrate using solder reflow technology even if the optical subassemblies are composed of materials that are not reflow compatible.

Abstract: A method includes receiving a first target pattern of an integrated circuit (IC) that includes two first target features and two second target features. The method further includes deriving a second target pattern based on the first target pattern and a directed self-assembly (DSA) process, wherein the first target pattern is to be produced by a process that includes performing the DSA process with a guide pattern derived from the second target pattern. The second target pattern includes a third feature and a fourth feature. The third feature is designed for producing the two first target features with the DSA process, and the fourth feature is designed for producing the two second target features with the DSA process. The method further includes inserting one or more sub-DSA-resolution assistant features (SDRAF) into the second target pattern, the one or more SDRAF connecting the third and fourth features.