Patents by Inventor Jie Wu

Jie Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250023256
    Abstract: An antenna device and a wireless mobile terminal. The antenna device includes: a frame including a border and a hollow space surrounded and formed by the border; a support connected to the border and extending towards the hollow space; and an antenna assembly including a first antenna module and a second antenna module. The first antenna module is arranged on the support and includes a plurality of first antenna units distributed at intervals, and the second antenna module includes a plurality of second antenna units. The first antenna module and the support are insulated from each other, and the support includes a conductive material and is reused as at least a portion of the second antenna units.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Applicants: Yungu (Gu’an) Technology Co., Ltd., Hefei Visionox Technology Co., Ltd.
    Inventors: Huan-Chu HUANG, Jie WU, Shuang CUI
  • Publication number: 20250001368
    Abstract: This disclosure concerns a method of forming a covalent organic framework (COF) membrane, comprising forming a membrane substrate by impregnating a porous polymer with a pore-forming agent in order to form an impregnated polymer, at least partially carbonising the impregnated polymer at a temperature of about 150° C. to about 500° C. in order to form the membrane substrate, and interfacially polymerising amino monomers and acyl monomers on a surface of the membrane substrate in order to form the COF membrane. The membrane substrate is characterised by a crystallinity of about 10% to about 70% relative to the porous polymer. The disclosure also concerns the COF membrane thereof, and the use of the COF membrane in catalyst recovery.
    Type: Application
    Filed: July 27, 2022
    Publication date: January 2, 2025
    Inventors: DAN ZHAO, Hao YANG, Jie WU, Jinhui XU
  • Publication number: 20250003917
    Abstract: A method for producing an electrochemiluminescence nanoprobe according to an embodiment includes: a Pdots nanoparticle synthesis step of synthesizing a Pdots nanoparticle by polymerizing a conjugated polymer and a copolymer molecule; and a Pdots nanoparticle modification step of modifying a resulting Pdots nanoparticle using an oligonucleotide chain modified with a quencher molecule.
    Type: Application
    Filed: June 10, 2024
    Publication date: January 2, 2025
    Applicants: CANON MEDICAL SYSTEMS CORPORATION, Nanjing University
    Inventors: Xiaotian WU, Qiqi XU, Hao HUANG, Huangxian JU, Jie WU
  • Publication number: 20250008260
    Abstract: Disclosed are an audio electronic device and a wind noise control method for a microphone of the audio electronic device. The wind noise control method for the microphone of the audio electronic device comprises: obtaining wind noise picked up by the microphone at a current position of the microphone; and in response to that the wind noise at the current position is greater than a first set value, controlling the driving device to drive the microphone until the wind noise at the current position of the microphone is less than a second set value, wherein the second set value is less than or equal to the first set value.
    Type: Application
    Filed: September 13, 2024
    Publication date: January 2, 2025
    Inventors: Zongxia ZHU, Kang AN, Jie WU
  • Publication number: 20240425751
    Abstract: A method for producing an electrochemiluminescence nanoprobe according to an embodiment includes: a hot exciton nanoparticle synthesis step of polymerizing a hot exciton organic luminescent molecule and a copolymer molecule to synthesize hot exciton nanoparticles; and a hot exciton nanoparticle modification step of modifying the obtained hot exciton nanoparticles with an oligonucleotide chain modified with a quencher molecule to obtain modified hot exciton nanoparticles.
    Type: Application
    Filed: June 10, 2024
    Publication date: December 26, 2024
    Applicants: CANON MEDICAL SYSTEMS CORPORATION, Nanjing University
    Inventors: Xiaotian WU, Qiqi XU, Hao HUANG, Chao WANG, Huangxian JU, Jie WU
  • Publication number: 20240416808
    Abstract: The present application provides a support structure, including: a support body; and at least one buffer portion, provided within the support body, where the buffer portion includes a plurality of buffer blocks provided adjacent to each other; where at least one first slit is provided on a support surface of the buffer portion, the first slit divides the buffer portion into the plurality of the buffer blocks, and the plurality of the buffer blocks are connected to each other at at least one position of the buffer portion other than the support surface. The present application further provides a seat cushion structure and a child safety seat.
    Type: Application
    Filed: June 10, 2024
    Publication date: December 19, 2024
    Inventors: Xiaolong MO, Kun ZHANG, Jie WU
  • Publication number: 20240421762
    Abstract: Disclosed are a power device and a photovoltaic power generation device. The power device comprises a case, a first power board, and a second power board, the first power board is arranged in the case, and a first boosting module and an inverter module are arranged on the first power board; the second power board is arranged in the case, the second power board is electrically connected to the first power board, and a second boosting module is arranged on the second power board. According to the technical solution of the present invention, the rated power generation power of the photovoltaic power generation device can be increased, and the flexibility for clients is improved.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 19, 2024
    Inventors: Yonghong LI, Yongfu WU, Wenhao LI, An’an XU, Jie WU, Weifeng ZHANG, Lei SHI
  • Publication number: 20240412480
    Abstract: Provided in the present disclosure are an image segmentation label generation method and apparatus, and an electronic device and a storage medium. The image segmentation label generation method includes: acquiring a feature map of an original image, determining a feature response map of the feature map, wherein a response value in the feature response map represents a weight of a corresponding feature in the feature map in image classification; increasing a response value within a preset range in the feature response map, reconstructing the feature map according to a feature response map with the increased response value; determining a first-class activation mapping based on the first reconstructed feature map, and determining an image segmentation label according to the first-class activation mapping.
    Type: Application
    Filed: December 1, 2022
    Publication date: December 12, 2024
    Inventors: Jie Wu, Jie Qin, Xuefeng Xiao
  • Publication number: 20240404418
    Abstract: The present application provides a VR-based standardized training system for multi-person online cooperated first-aid nursing of trauma, which is used for providing medical staff with an efficient and convenient-to-update and maintain standardized training environment for multi-person online cooperated first-aid nursing of trauma by introducing the VR technology, so as to significantly improve the training effect of the first aid of trauma of the medical staff.
    Type: Application
    Filed: April 26, 2024
    Publication date: December 5, 2024
    Applicant: Tongji Hospital affiliated to Tongji Medical College of Huazhong University of Science & Technology
    Inventors: Jing CHENG, Huibing CHEN, La XIE, Yaru XIAO, Xiangping LIU, Jie WU, Zheying LI, Hui WU, Jingjing FU
  • Publication number: 20240379418
    Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Feng-Cheng YANG, Chung-Te LIN
  • Patent number: 12142838
    Abstract: Embodiments of the present disclosure relate to a phased-array antenna, a display panel, and a display device. The phased-array antenna includes a first substrate and a second substrate arranged oppositely, and a plurality of phased-array elements located between the first substrate and the second substrate. At least one of the phased-array elements includes a first electrode, a second electrode arranged opposite to the first electrode, a voltage-controlled phase shift material located between the first electrode and the second electrode, wherein the first electrode is configured to receive a bias signal for controlling the voltage-controlled phase shift material, and the second electrode serves as a ground electrode, and a microstrip line located at a side of the first electrode far away from the voltage-controlled phase shift material and electrically insulated from the first electrode, wherein the microstrip line is configured to receive or transmit a transmission signal.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 12, 2024
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xue Cao, Tien-Lun Ting, Jie Wu, Ying Wang, Chuncheng Che, Hailin Xue
  • Patent number: 12139647
    Abstract: Provided is a composition comprising one or more epoxy phosphate esters wherein the structure comprises two or more polyester linkages. Also provided is a method of making the epoxy phosphate esters that comprises reacting one or more epoxy-terminated polyesters with one or more phosphoric acids. Further provided is an adhesive composition that comprises one or more epoxy phosphate esters, one or more multifunctional isocyanate prepolymers, and one or more multifunctional isocyanate-reactive compounds.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: November 12, 2024
    Assignees: Dow Global Technologies LLC, Rohm and Haas Company
    Inventors: Tuoqi Li, Joseph J. Zupancic, Yinzhong Guo, Jie Wu
  • Publication number: 20240373646
    Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 7, 2024
    Inventors: Hui-Hsien WEI, Yen-Chung HO, Chia-Jung YU, Yong-Jie WU, Pin-Cheng HSU
  • Publication number: 20240372004
    Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Feng-Cheng YANG, Chung-Te LIN
  • Publication number: 20240373650
    Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: HUI-HSIEN WEI, YEN-CHUNG HO, CHIA-JUNG YU, YONG-JIE WU, PIN-CHENG HSU
  • Publication number: 20240363762
    Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Yong-Jie Wu, Hui-Hsien Wei, Yen-Chung Ho, Mauricio Manfrini, Chia-Jung Yu, Chung-Te Lin, Pin-Cheng Hsu
  • Patent number: 12125921
    Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Hui-Hsien Wei, Yen-Chung Ho, Mauricio Manfrini, Chia-Jung Yu, Chung-Te Lin, Pin-Cheng Hsu
  • Publication number: 20240348138
    Abstract: A vibration motor is provided, including: a housing including a pair of side walls, a vibrator including a mass block, a pair of elastic support members disposed at both ends of the vibrator, and a stator. The mass block includes a pair of corners diagonally disposed. Each corner includes a first side edge, a second side edge, and a beveled edge. Each elastic support member includes a first fixing portion fixed to a respective beveled edge, a straight edge portion curved and extending from the first fixing portion in a direction away from a respective first side edge and close to a respective second side edge, a second fixing portion fixed to a respective side wall away from the corresponding corner, and a curved portion connecting the straight edge portion and the second fixing portion. The vibration motor in the present disclosure is capable of improving performance.
    Type: Application
    Filed: December 26, 2023
    Publication date: October 17, 2024
    Inventors: Weibo Chen, Xiaorong Zhou, Ziyang Zhang, Jie Wu
  • Publication number: 20240345257
    Abstract: A mobile device includes: a user input device; a satellite positioning system (SPS) receiver; a wireless communication signal transceiver; at least one motion sensor; and a processor communicatively coupled to the user input device and the SPS receiver, the processor being configured to: receive, from the user input device, a swimming indication of swimming by a user; and determine, in response to the swimming indication, a swimming stroke status based on one or more signals received by the SPS receiver.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 17, 2024
    Inventors: Jie WU, Robert Dale THRASHER, Jeffrey WONG, Krishnaranjan RAO
  • Publication number: 20240349514
    Abstract: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Mauricio MANFRINI, Chung-Te LIN