Patents by Inventor Jiehui SHU

Jiehui SHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10510613
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xusheng Wu, Haigou Huang, John H. Zhang, Pei Liu, Laertis Economikos
  • Publication number: 20190378751
    Abstract: A finFET device is disclosed including a fin defined in a semiconductor substrate, the fin having an upper surface and a first diffusion break positioned in the fin, wherein the first diffusion break comprises an upper surface that is substantially coplanar with the upper surface of the fin.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Jiehui Shu, Hong Yu, Jinping Liu, Hui Zang
  • Publication number: 20190371796
    Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Garo Jacques Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey
  • Publication number: 20190363174
    Abstract: Methods form transistor devices that have source/drain regions in a layer separated by a channel region. A gate conductor is above the channel region and has sidewalls extending from the top surface of the layer. First spacers are formed to contact the sidewalls of the gate conductor. The first spacers are formed to have top portions that are relatively distal to the surface of the layer, and bottom portions that are relatively adjacent to the surface of the layer. Second spacers are formed to contact the top portions of the first spacer. Conductive contacts are formed to connect to the source/drain regions. The bottom portions of the first spacers are formed to contact and be between the conductive contacts and the gate conductor. The second spacers are formed between the top portions of the first spacers and the conductive contacts.
    Type: Application
    Filed: May 24, 2018
    Publication date: November 28, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Jiehui Shu, Shesh Mani Pandey, Laertis Economikos
  • Publication number: 20190363180
    Abstract: A finFET structure includes an insulative cap over each gate in a vicinity of a first and second self-aligned contact (SAC) to source/drain regions thereof. The insulative cap has a bulbous upper insulative cap portion selectively grown to protect gate height loss during SAC opening formation. The bulbous upper insulative cap portion may be over just gates in the vicinity of the S/D regions, and optionally, over gates in the vicinity of a gate contact.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Inventors: Hui Zang, Ruilong Xie, Jiehui Shu
  • Publication number: 20190355624
    Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
  • Publication number: 20190355832
    Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 21, 2019
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Publication number: 20190355615
    Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Jiehui Shu, Garo Jacques Derderian, Hui Zang, John Zhang, Haigou Huang, Jinping Liu
  • Publication number: 20190355658
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Inventors: Ravi Prakash Srivastava, Hui Zang, Jiehui Shu
  • Patent number: 10475791
    Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Garo Jacques Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey
  • Patent number: 10475693
    Abstract: A method includes forming a first hard mask layer above a substrate. The first hard mask layer is patterned to define a plurality of fin openings and at least a first diffusion break opening. A first etch process is performed to define a plurality of fins in the substrate and a first diffusion break recess in a selected fin. A first dielectric layer is formed between the fins and in the first diffusion break recess to define a first diffusion break. A second hard mask layer having a second opening positioned above the first diffusion break is formed above the first hard mask layer and the first dielectric layer. A second dielectric layer is formed in the second opening. The second hard mask layer is removed. A second etch process is performed to recess the first dielectric layer to expose upper portions of the plurality of fins.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Hong Yu, Jinping Liu, Hui Zang
  • Publication number: 20190341475
    Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.
    Type: Application
    Filed: May 3, 2018
    Publication date: November 7, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Laertis Economikos, Xusheng Wu, John Zhang, Haigou Huang, Hui Zhan, Tao Han, Haiting Wang, Jinping Liu, Hui Zang
  • Publication number: 20190333993
    Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.
    Type: Application
    Filed: April 25, 2018
    Publication date: October 31, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Ruilong Xie, Hui Zang, Haiting Wang
  • Publication number: 20190326416
    Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.
    Type: Application
    Filed: April 18, 2018
    Publication date: October 24, 2019
    Inventors: Haigou Huang, Jiehui Shu, Chih-Chiang Chang, Xingzhao Shi, Jinsheng Gao, Huy Cao
  • Publication number: 20190326209
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung M. Chae, Jinping Liu, Hui Zang
  • Patent number: 10453936
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Publication number: 20190318931
    Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 17, 2019
    Inventors: Jiehui Shu, Xiaohan Wang, Qiang Fang, Zhiguo Sun, Jinping Liu, Hui Zang
  • Patent number: 10446395
    Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xiaohan Wang, Qiang Fang, Zhiguo Sun, Jinping Liu, Hui Zang
  • Publication number: 20190304843
    Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
  • Patent number: 10431500
    Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu