Patents by Inventor Jiehui SHU

Jiehui SHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160365277
    Abstract: A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Inventors: Qiang FANG, Zhiguo SUN, Jiehui SHU
  • Patent number: 9275898
    Abstract: Methods of forming a Co cap on a Cu interconnect in or through an ULK ILD with improved selectivity while protecting an ULK ILD surface are provided. Embodiments include providing a Cu filled via in an ULK ILD; depositing a Co precursor and H2 over the Cu-filled via and the ULK ILD, the Co precursor and H2 forming a Co cap over the Cu-filled via; depositing an UV cured methyl over the Co cap and the ULK ILD; performing an NH3 plasma treatment after depositing the UV cured methyl; and repeating the steps of depositing a Co precursor through performing an NH3 plasma treatment to remove impurities from the Co cap.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: March 1, 2016
    Inventors: Jiehui Shu, Zhiguo Sun, Yang Bum Lee, Huang Liu
  • Publication number: 20150325445
    Abstract: An improved method for fabricating a semiconductor device is provided to decrease substrate gouging during oxide spacer formation. The method includes: forming a gate structure on a substrate; depositing an oxide layer along the sidewalls of the gate structure and on the substrate; removing some of the oxide layer to define oxide spacers along sidewalls of the gate structure; and performing an isotropic etch process to remove a residual portion of the oxide layer.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 12, 2015
    Inventors: Jiehui SHU, Huang LIU
  • Publication number: 20090315121
    Abstract: An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric (PMD) layer is disposed over the substrate and the transistor. At least one of the isolation region or the PMD layer includes O3-TEOS having a first stress. A cap layer is disposed over the O3-TEOS in the isolation region or the PMD layer. The cap layer prevents degradation of the first stress of the O3-TEOS.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Luona GOH, Jeff Jiehui SHU, Huang LIU, Wei LU