Abstract: A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

Abstract: A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

Abstract: A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrate between the drain and the source. The gate includes a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer. The transistor includes at least one empty side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.

Abstract: The present invention provides a MOS (metal-oxide-semiconductor) transistor with two empty side slots on its gate and method for forming the same. The MOS transistor comprises a substrate, an insulation layer, a gate and a dielectric layer. The substrate has a surface layer which comprises a drain and a source separately positioned on two separate areas of the surface layer. The insulation layer positioned on the surface of the substrate between the drain and the source. The gate comprises a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer for reducing resistance of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.

Abstract: A method of reducing junction capacitance. In a doped substrate or well, a super steep counter-doped implantation is performed, so as to form a super steep counter-doped region beneath the source/drain region in the substrate. As a consequence, the region near the source/drain region has a reduced doping concentration, and the junction capacitance of the source/drain region is reduced.

Abstract: The present invention provides a method of forming a Metal Oxide Semiconductor (MOS) transistor on a substrate of a semiconductor wafer. A gate of the MOS transistor is formed on the substrate. A source and a drain of the MOS transistor are then formed in the substrate. An ion implantation process is performed to form a first doped region, a second doped region and a third doped region. The first doped region is positioned under the gate and overlaps with the channel of the MOS transistor. The second doped region is positioned in a predetermined portion of the substrate under the source. The third doped region is positioned in a predetermined portion of the substrate under the drain. The first doped region, the second doped region, the third doped region, the source, and the drain are all of the same type of semiconductor.

Abstract: A SEG combined with tilt implant method for forming semiconductor device is disclosed. The method includes providing a semiconductor structure which comprises an active area in between isolation regions in a substrate with the active area having a gate electrode formed thereon, wherein a spacer is formed on the sidewall of said gate electrode. Then, selective epitaxial growth regions are formed on the active area and the gate electrode. Next, the active area is implanted with an angle to form source/drain regions beside the bottom edge of the gate electrode. Then, the salicide process and backend processes are performed.

Abstract: A method of polishing a polysilicon layer by using a chemical mechanical polishing process is described. A semiconductor substrate is provided, and a shallow trench isolation structure is formed on the semiconductor substrate such that the substrate has an uneven surface. A first polysilicon layer is formed on the semiconductor substrate and the shallow trench isolation structure. A polishing step is performed on the first polysilicon layer to planarize the first polysilicon layer. A second polysilicon layer is formed on the first polysilicon layer, wherein an interface is formed between the second polysilicon layer and the first polysilicon layer.

Abstract: The present invention provides a method of forming a MOS transistor on a substrate of a semiconductor wafer. The method comprises forming a rectangular-shaped gate on the substrate, forming a spacer at each of two opposite sides of the gate on the substrate, performing a first ion implantation process to form a source and a drain at predetermined positions of the substrate beside the two spacers, performing a first thermal annealing process on the semiconductor wafer, removing the spacers from the two sides of the gate, performing a second ion implantation process on the substrate to form a conducting layer below each of the spacers wherein one conducting layer is electrically connected with the source and another conducting layer is electrically connected with the drain, and performing a second thermal annealing process on the semiconductor wafer for activating implants of the second ion implantation process in the two conducting layers.

Abstract: A method for forming MOSFET is disclosed. The method includes firstly providing a substrate, on which a gate without spacer is already formed. A first spacer is formed on sidewall of the gate, a lightly doped drain is subsequently formed in the substrate. Next, a second spacer is formed on the first spacer. Finally, a heavily doped drain is formed in the substrate. The present invention can enhance stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract: A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming wells in the substrate, two implantation regions for providing a threshold voltage (VT) adjustment and an anti-punch through layer are formed respectively in a P-well and a N-well of the core region as well as a P-well and a N-well of the I/O region. The method involves forming a pattern mask on the gate oxide layer, wherein the pattern mask has an opening, which may be a channel that corresponds to the P-well of the core region. With the pattern mask serving as an ion implantation mask, two implantation regions for providing the VT adjustment and the anti-punch through layer are formed in the P-well of the core region. After the pattern mask is removed, the steps described above are repeated in order to form implantation regions in other regions, but the sequence of the steps can be swapped around at will.

Abstract: A method for forming a semiconductor structure by using super halo implant combined with offset spacer process is disclosed. This invention comprises providing a substrate with a gate electrode formed thereon and a halo implant region formed therein. Then, a dielectric layer is deposited on the substrate and the gate electrode. Next, the semiconductor structure is annealed, and the dielectric layer is anisotropically etched to form an offset spacer.

Abstract: A method for forming a MOS transistor is provided. A gate oxide layer, a polysilicon layer, a barrier layer and a conductive layer are sequentially formed on a provided substrate. A photolithography and etching process is carried out to remove a portion of the conductive layer and a portion of the barrier layer until exposing the polysilicon layer. An ion implantation is performed to form lightly doped regions in the substrate using the remaining conductive layer and the remaining barrier layer as a mask. A spacer is formed on the side-wall of the conductive layer and on the side-wall of the barrier layer. The polysilicon layer and the gate oxide layer, which are in positions other than those of the remaining conductive layer and the spacer, are removed. The remaining conductive layer and the remaining polysilicon layer constitute a gate with an inversed, T-shaped cross-section.

Abstract: A method for forming borderless contact capable of reducing junction leakage current by forming a deep junction in the source/drain region nearest the borderless contact to eliminate most of the leakage current. The method includes the steps of first forming a shallow trench isolation structure for isolating devices in a semiconductor substrate. In the subsequent step, an ion implantation is carried out implanting ions at a small tilt angle to form source/drain regions such that source/drain region nearest to the shallow trench isolation structure has a deep junction. Finally, a borderless opening is formed above the source/drain region and the shallow trench isolation structure, and then conductive material is deposited into the borderless opening to form the borderless contact.

Abstract: A method of suppressing junction capacitance of the source/drain regions is disclosed in this invention. The source/drain regions are formed by double implantation of phosphorus ions and arsenic ions. The phosphorus ion implantation lowers the energy needed in the implantation of arsenic ions, and reduces dislocations in the source/drain regions formed during implanting arsenic ions. Further, the double implantation suppresses the junction profile of arsenic ions, and enhances the width of depletion regions. So, the junction capacitance is reduced, thereby accelerate the function of semiconductor devices.

Abstract: A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer.

Abstract: A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

Abstract: A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed.

Abstract: A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.