Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.

Abstract: A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.

Abstract: A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes a semiconductor substrate which is provided and forms a gate oxide layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, pattern transfers onto the photoresist layer after going through an exposure and a development. Furthermore, the gate layer and the gate oxide layer are then etched by using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin nitride oxide (NO, N2O) layer is grown by utilizing rapid thermal oxidation (RTO) and rapid thermal nitridation (RTN). Hereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A TEOS layer and a silicon nitride layer are deposited by using LPCVD, and forming spacers by etching the silicon nitride layer and the TEOS layer.

Abstract: A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.

Abstract: A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening.

Abstract: A method is described for manufacturing a shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench penetrates through the mask layer and the pad oxide layer and into the substrate. A liner oxide layer is formed on a portion of the sidewall of the trench in the substrate. A silicon layer is formed in the trench with a same surface level as the interface between the substrate and the pad oxide layer and an insulating layer is formed on the silicon layer.

Abstract: A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.

Abstract: A method of fabricating a metal oxide semiconductor includes formation of a gate on a substrate. A source/drain extension is formed beside the gate in the substrate. An ion implantation step is performed to implant heavy impurities with a low diffusion coefficient in the substrate. A heavily doped halo region is formed in the substrate below the source/drain extension. A tilt-angled halo implantation step is performed to form a halo-implanted region in the substrate to the side of the source/drain extension below the gate.

Abstract: The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffsion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide.

Abstract: A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer.

Abstract: A method for cleaning a silicon wafer. The method includes intentionally exposing the wafer into a volatile solvent with a polarity between about 2 and 4, whereby the wafer is cleaned by the solvent such that the formation of silicon recesses in source/drain extension regions on the silicon wafer can be prevented or avoided.

Abstract: A semiconductor read-only memory (ROM) device is provided and includes an array of diode-based memory cells for storing binary data. Whether a memory cell of the ROM device is set to a permanently-ON or OFF state, depends upon whether the memory cell is formed with a junction diode, wherein the presence of a junction diode in the memory cell causes the memory cell to be set to a permanently-ON state. Formation of the junction diode includes the step of forming a plurality of parallel-spaced first diffusion regions of a semiconductor type, to serve as a plurality of bit lines. An insulating layer is then formed to cover the first diffusion regions. A plurality of contact windows are formed at predefined locations of the insulating layer where a first group of memory cells, set to a permanently-ON state, are formed. The unexposed portions of the first diffusion regions are associated with a second group of memory cells that are set to a permanently-OFF state.

Abstract: A structure of a spacer in a semiconductor device is disclosed. Firstly, a gate without a spacer is provided on a substrate. A first insulating layer is formed on the sidewall of the gate. After a lightly doped drain is subsequently achieved in the substrate, a second insulating layer is formed on the first spacer. The process following this embodiment described above is to form a heavily doped drain in the substrate, then the whole MOSFET fabrication is completed. The present invention can enhance the stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract: A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.

Abstract: A method fabricating salicide. A substrate having a polysilicon gate and a source/drain region is provided. A silicon oxide layer is formed on the polysilicon gate and the substrate. Using dry etch, a part of the silicon oxide layer is removed to leave a spacer with a waistline on a side wall of the polysilicon gate. A metal layer is formed on the polysilicon gate and the source/drain region.

Abstract: A method for forming devices having a thick gate oxide. The method comprises the steps of providing a substrate having different device areas already defined thereon through shallow trench isolation, then forming a first gate oxide layer over the substrate. Next, a silicon nitride layer is formed over the first gate oxide layer, then patterned using a mask to selectively expose the first gate oxide layer in the thick gate oxide area. Subsequently, a thermal oxidation is performed to directly grow an oxide layer over the first gate oxide layer to form a thicker second gate oxide layer. Since no gate oxide layer is removed in this invention, the distribution of ions implanted in previous processing steps will remain unchanged. Therefore, the fabricated devices will have more stable properties and better reliability.

Abstract: A method of fabricating a MOS FET is provided. An oxide layer and a polysilicon layer are successively formed on the semiconductor substrate. A pyramidical photoresist layer is used as a mask for forming a hat-shaped gate structure. A first ion implantation process is performed to form an LDD structure.

Abstract: A method for forming a dual gate oxide layer, which can be suitably applied to the surface of a shallow trench isolation structure, comprising the steps of providing a substrate that has a device isolation structure already formed thereon such as a shallow trench isolation. Next, a thermal oxidation process is carried out to form an oxide layer over the substrate and the isolation structure. A silicon nitride layer is then deposited on top of the oxide layer. In the subsequent step, the silicon nitride layer is patterned to cover portions of the oxide layer that lies in an input/output area. The method of this invention produces a better quality gate oxide layer over the device isolation structure and the substrate surface. Therefore, device problems caused by the deposition of a poor quality gate oxide in a conventional method can be greatly reduced.

Abstract: A method of fabricating an air-gap spacer of a metal-oxide-semiconductor device includes the following steps. First, a substrate having a gate oxide layer and a polysilicon layer successively formed is provided. The polysilicon layer and the gate oxide layer are patterned to form a gate electrode region. A silicon nitride layer and an oxide layer are successively formed on the surface of the substrate and the surface of the gate electrode region. The oxide layer and the silicon nitride layer are anisotropically etched to form a cross-sectional L-shaped silicon nitride layer and a first spacer at the sidewall of the gate electrode region. After the first spacer is removed, an ion implantation is performed to form an extended lightly doped region below the L-shaped silicon nitride layer in the substrate and a lightly doped region in the substrate surrounding the extended lightly doped region.