Abstract: A method for forming a dual gate oxide layer, which can be suitably applied to the surface of a shallow trench isolation structure, comprising the steps of providing a substrate that has a device isolation structure already formed thereon such as a shallow trench isolation. Next, a thermal oxidation process is carried out to form an oxide layer over the substrate and the isolation structure. A silicon nitride layer is then deposited on top of the oxide layer. In the subsequent step, the silicon nitride layer is patterned to cover portions of the oxide layer that lies in an input/output area. The method of this invention produces a better quality gate oxide layer over the device isolation structure and the substrate surface. Therefore, device problems caused by the deposition of a poor quality gate oxide in a conventional method can be greatly reduced.

Abstract: A method of fabricating an air-gap spacer of a metal-oxide-semiconductor device includes the following steps. First, a substrate having a gate oxide layer and a polysilicon layer successively formed is provided. The polysilicon layer and the gate oxide layer are patterned to form a gate electrode region. A silicon nitride layer and an oxide layer are successively formed on the surface of the substrate and the surface of the gate electrode region. The oxide layer and the silicon nitride layer are anisotropically etched to form a cross-sectional L-shaped silicon nitride layer and a first spacer at the sidewall of the gate electrode region. After the first spacer is removed, an ion implantation is performed to form an extended lightly doped region below the L-shaped silicon nitride layer in the substrate and a lightly doped region in the substrate surrounding the extended lightly doped region.

Abstract: A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device.

Abstract: A method for fabricating a MOS transistor device is provided. The method contains sequentially forming an oxide layer, a polysilicon layer, and a cap layer over a semiconductor substrate. Patterning the oxide layer, the polysilicon layer, the cap layer, and the substrate forms a trench opening in the substrate. A shallow trench isolation (STI) structure is formed by filling the opening with insulating material. A first-stage gate structure is formed on the substrate by patterning the oxide layer, the polysilicon layer, and the cap layer. A top portion of the STI structure above the substrate surface is exposed. A light ion implantation is performed to form a lightly doped region. Several spacers are respectively formed on each sidewall of the first-stage gate structure and each exposed sidewall of the STI structure. A heavy ion implantation process is performed to form interchangeable source/drain regions at each side of the first-stage gate structure. The cap layer is removed to leave an opening.

Abstract: An air-gap spacer of a metal-oxide-semiconductor device comprises a spacer and a cross-sectional L-shaped air-gap. The spacer is adjacent to a sidewall of the gate electrode but not directly contacts to the gate electrode. The cross-sectional L-shaped air-gap is located between the spacer and the gate electrode and between the spacer and the substrate so that the spacer is separated from the gate electrode and the spacer is partially separated from the substrate.

Abstract: A method is provided for fabricating a read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented.

Abstract: A method for forming shallow trench isolation comprising the steps of providing a substrate having a mask layer formed thereon. Next, the mask layer is patterned to form a first trench in the substrate. Then, dielectric spacers are formed on the sidewalls of the first trench. After that, a second trench is formed in the substrate by an etching operation following the profile of the dielectric spacers. Next, a second dielectric layer is formed filling the second trench, wherein the second dielectric layer and the dielectric spacers are formed from different materials. Thereafter, the dielectric spacers are removed to form recess cavities, and then a filler material is deposited into the recess cavities. Subsequently, a gate oxide layer is formed over the filler material and the substrate. Finally, a polysilicon gate layer is formed over the gate oxide layer.

Abstract: A ROM device of the type including an array of diode-type memory cells and a method for fabricating the same are provided. The bit lines of this ROM device are a plurality of diffusion regions formed in an alternate manner on the bottom of a plurality of parallel-spaced trenches and on the top of the solid portions between these trenches. This particular arrangement of the bit lines allows for an increased integration of the diode-type memory cells on a limited wafer surface without having to reduce the feature size of the semiconductor components of the ROM device. The diode-type memory cells that are set to a permanently-ON state involve a P-N junction diode being formed therein, wherein the P-N junction diode is electrically connected via a contact window in an insulating layer to the associated one of the overlaying word lines. Other memory cells that are set to a permanently-OFF state are formed with no P-N junction diode therein.

Abstract: A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed.

Abstract: The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffusion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide.

Abstract: A method of fabricating a metal-oxide semiconductor (MOS) transistor is provided. This method is devised particularly to reduce the level of degradation to the MOS transistor caused by hot carriers. In the fabrication process, a plasma treatment is applied to the wafer to as to cause the forming of a thin layer of silicon nitride on the wafer which covers the gate and the lightly-doped diffusion (LDD) regions on the source/drain regions of the MOS transistor. This thin layer of silicon nitride acts as a barrier which prevents hot carriers from crossing the gate dielectric layer, such that the degradation of the MOS transistor due to hot carriers crossing the gate dielectric layer can be greatly minimized.

Abstract: A method of fabricating flat-cell mask ROM devices having buried bit-lines that will not be subject to punch-through between neighboring bit lines as a result of heating in subsequent steps after the buried bit-lines are formed. In the method, the first step is to prepare a semiconductor substrate with a gate oxide layer formed thereon. Thereafter, a first polysilicon layer is formed over the gate oxide layer, and a plurality of trenches at predetermined positions, with these trenches extending through the gate oxide and first polysilicon layer and into the substrate to a predetermined depth. Then, trenches are filled with tungsten to form a plurality of source/drain regions. A second polysilicon layer is then formed over the first polysilicon layer, and an insulating layers is formed over each of the source/drain regions.

Abstract: A diode-based ROM device and a method for fabricating the same are provided. The ROM device is of the type including an array of diode-based memory cells for permanent storage of binary-coded data therein. In the semiconductor structure of the ROM device, a plurality of insulator-filled trenches are formed for isolation of the diode-based memory cells. This feature allows the prevention of the punch-through effect when the ROM device is downsized. Further, the bit lines for the ROM device are formed with an increased junction depth such that the resistance of the bit lines can be reduced to allow an increase in the magnitude of the currents in the bit lines for easier detection and distinguishing of the binary state the currents represent.

Abstract: A ROM device of the type including an array of diode-type memory cells and a method for fabricating the same are provided. The bit lines of this ROM device are a plurality of diffusion regions formed in an alternate manner on the bottom of a plurality of parallel-spaced trenches and on the top of the solid portions between these trenches. This particular arrangement of the bit lines allows for an increased integration of the diode-type memory cells on a limited wafer surface without having to reduce the feature size of the semiconductor components of the ROM device. The diode-type memory cells that are set to a permanently-ON state involve a P-N junction diode being formed therein, wherein the P-N junction diode is electrically connected via a contact window in an insulating layer to the associated one of the overlaying word lines. Other memory cells that are set to a permanently-OFF state are formed with no P-N junction diode therein.

Abstract: A method of forming MOS components provides that after the formation of the gate and the doped source/drain regions, a polysilicon layer is deposited and planarized using a chemical-mechanical polishing method. The resulting unremoved polysilicon layer acts as source/drain terminals. Through these arrangements, the ion doped source/drain regions will have shallow junctions, yet their junction integrity will not be compromised by subsequent contact window etching and metallization processes. Furthermore, the front-end processes for forming the MOS component provide a good planar surface that offers great convenience for the performance of subsequent back-end processes.

Abstract: The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.