Patents by Inventor Jimmy Fort

Jimmy Fort has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120293149
    Abstract: An adjustable bandgap reference voltage comprises means for generating current proportional to absolute temperature comprising first means connected to terminals of a core and designed to equalize voltages across the terminals, means for generating a current inversely proportional to absolute temperature connected to the core, and an output module designed to generate the reference voltage; the first processing means comprise a first amplifier possessing a stage, biased by the current inversely proportional to absolute temperature, arranged according to a folded setup and comprising first PMOS transistors arranged according to a common-gate setup, and a stage whose input is connected to the amplifier output and whose output is connected to the first stage input and to a terminal of the core, the second generating means comprise a follower amplifier setup connected to a terminal of the core and separated from the first amplifier, the output module is connected to the feedback stage.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 22, 2012
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Patent number: 8270242
    Abstract: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: September 18, 2012
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Thierry Soude, Nicolas Zammit
  • Publication number: 20120161873
    Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).
    Type: Application
    Filed: March 7, 2012
    Publication date: June 28, 2012
    Applicant: ATMEL ROUSSET S.A.S.
    Inventors: Jimmy Fort, Thierry Soude, Michel Cuenca, Florent Garcia, Franck Strazzieri
  • Patent number: 8183922
    Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: May 22, 2012
    Assignee: Atmei Rousset S.A.S.
    Inventors: Jimmy Fort, Thierry Soude, Michel Cuenca, Florent Garcia, Franck Strazzieri
  • Patent number: 8169845
    Abstract: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell; and a second circuit including a second circuit path coupled between the supply node and the line to charge the line during the memory operation. Additional embodiments are disclosed.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: May 1, 2012
    Assignee: Atmel Corporation
    Inventor: Jimmy Fort
  • Patent number: 8067975
    Abstract: A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: November 29, 2011
    Assignee: Atmel Corporation
    Inventor: Jimmy Fort
  • Patent number: 8054156
    Abstract: This document discloses low variation resistor devices, methods, systems, and methods of manufacturing the same. In some implementations, a low-variation resistor can be implemented with a metal-oxide-semiconductor field-effect-transistor (“MOSFET”) operating in the triode (e.g., ohmic) region. The MOSFET can have a source that is connected to a reference voltage (e.g., ground) and a gate connected to a gate voltage source. The gate voltage source can generate a gate voltage that varies in proportion to changes in the temperature of an operating environment. The gate voltage variation can, for example, be controlled so that it offsets the changes in MOSFET resistance that are caused by changes in temperature. In some implementations, the gate voltage variation offsets the resistance variance by offsetting changes in transistor mobility that are caused by changes in temperature.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: November 8, 2011
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Michel Cuenca
  • Patent number: 8031547
    Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: October 4, 2011
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Renaud Dura, Thierry Soude
  • Patent number: 8004924
    Abstract: A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: August 23, 2011
    Assignee: Atmel Corporation
    Inventors: Sylvain Leomant, Jimmy Fort, Arnaud Turier, Laurent Vachez, Lotfi B. Ammar
  • Publication number: 20110115560
    Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).
    Type: Application
    Filed: November 17, 2009
    Publication date: May 19, 2011
    Applicant: ATMEL ROUSSET SAS
    Inventors: Jimmy Fort, Thierry Soude, Michel Cuenca, Florent Garcia, Franck Strazzieri
  • Publication number: 20110026347
    Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.
    Type: Application
    Filed: October 8, 2010
    Publication date: February 3, 2011
    Applicant: ATMEL Corporation
    Inventors: Jimmy Fort, Renaud Dura, Thierry Soude
  • Publication number: 20100329059
    Abstract: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell; and a second circuit including a second circuit path coupled between the supply node and the line to charge the line during the memory operation. Additional embodiments are disclosed.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Applicant: Atmel Corporation
    Inventor: Jimmy Fort
  • Publication number: 20100329023
    Abstract: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Applicant: Atmel Corporation
    Inventors: Jimmy Fort, Thierry Soude, Nicolas Zammit
  • Patent number: 7813201
    Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 12, 2010
    Assignee: ATMEL Corporation
    Inventors: Jimmy Fort, Renaud Dura, Thierry Soude
  • Publication number: 20100208539
    Abstract: A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell.
    Type: Application
    Filed: February 18, 2009
    Publication date: August 19, 2010
    Applicant: Atmel Corporation
    Inventors: Sylvain Leomant, Jimmy Fort, Arnaud Turier, Laurent Vachez, Lotfi Ben Ammar
  • Publication number: 20100201430
    Abstract: A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference.
    Type: Application
    Filed: April 15, 2010
    Publication date: August 12, 2010
    Applicant: ATMEL CORPORATION
    Inventor: Jimmy Fort
  • Publication number: 20100127752
    Abstract: A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs.
    Type: Application
    Filed: November 24, 2008
    Publication date: May 27, 2010
    Applicant: ATMEL Corporation
    Inventors: Jimmy Fort, Michel Cuenca, Emmanuel Racape, Jean-Michel Daga
  • Patent number: 7719341
    Abstract: A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: May 18, 2010
    Assignee: ATMEL Corporation
    Inventor: Jimmy Fort
  • Patent number: 7683699
    Abstract: An improved charge pump design useful in low power applications derives an alternative voltage from a supply voltage. The design can be constructed using PMOS manufactured according to standard processes such that triple well manufacturing processes are not required. The design can incorporate control gate circuitry to increase efficiency and decrease degradation due to the threshold voltage of the transistors used.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 23, 2010
    Assignee: ATMEL Corporation
    Inventors: Jimmy Fort, Fabrice Siracusa
  • Patent number: 7679430
    Abstract: A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: March 16, 2010
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Fabrice Siracusa