Abstract: An apparatus for orbital angular momentum (OAM) mode combination and an antenna apparatus for multi-mode generation are provided. The apparatus for OAM mode combination includes three input ports configured to receive independent OAM mode signals, four output ports configured to output OAM mode signals with the same or different phase delays; and a circuit element configured to simultaneously combine or distribute the OAM mode signals by controlling phases of output signals output through the four output ports to be different depending on the OAM mode signals received through the input ports.

Abstract: Disclosed is a method of estimating a position of a signal source and a position estimation apparatus, the method including acquiring an environment, a frequency, and a bandwidth of the interference signal source, determining an arrangement form of the two antennas based on the environment, the frequency, and the bandwidth and arranging the two antennas, and estimating a position of the interference signal source based on an interference signal of the interference signal source and the two arranged antennas, wherein the environment includes an indoor environment and an outdoor environment.

Abstract: Provided is a video providing system. The video providing system includes a memory configured to store device information of a display device, an analyzer configured to receive an original video from the outside and analyze images in the original video, and a processor configured to generate, from the original video, video streams according to a streaming mode and control signals of the display device respectively corresponding to the video streams, based on device information of a display device and analysis information from the analyzer, and provide the video streams and the control signals to the display device.

Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.

Abstract: Provided is an energy charging apparatus including a transponder configured to transmit and receive radio energy, and a resonator configured to transmit the radio energy transmitted from the transponder to at least one external device and transmit the radio energy received from the at least one external device to the transponder, wherein each of the transponder and the resonator is provided in a form of a single module.

Abstract: A transceiving apparatus may comprise a radiator emitting a beam; a receiver receiving a beam; a first sub-reflector which is provided to face the radiator and changes an orbital angular momentum (OAM) mode order of a beam; a second sub-reflector which is provided to face the receiver and changes an OAM mode order of a beam differently from the first sub-reflector; and a main reflector which is provided to face the first sub-reflector and the second sub-reflector.

Abstract: The present disclosure relates to oncolytic viruses for use transcatheter arterial viroembolization methods. The present disclosure also provides composition with such oncolytic viruses in combination with a biocompatible microparticle or hydrophilic polymer gel agent suitable for active embolization. The present disclosure further provides methods of transcatheter arterial viroembolization using such oncolytic viruses and compositions preferably in a manner that debulks tumor.

Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.

Abstract: A buck converter that is efficient in power consumption is disclosed. A buck converter in accordance with an embodiment of the present invention includes an error amplifier and a comparator, at least one of which is powered and operated while a PWM signal is a high signal.

Abstract: Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.

Abstract: Disclosed is a circular array antenna. The circular array antenna includes: an input/output unit receiving electromagnetic waves from a transmitter and distributing the received electromagnetic waves to the antenna; a primary feeder connected with the input/output unit and placed at the center of the circular array antenna; a plurality of secondary feeders radially connected to the primary feeder; a plurality of patch units connected to the respective secondary feeders to generate an electric field radially; and a plurality of length controllers formed at terminals of the respective secondary feeders in a direction to extend the lengths of the respective secondary feeders, of which the lengths are controllable.

Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

Abstract: An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.

Abstract: An encoding apparatus in accordance with an embodiment of the present invention includes: an encoder configured to request for storage of an original frame; a frame processing unit configured to generate an encoded frame having the original framed encoded therein; and a frame memory configured to store the encoded frame. Here, the frame processing unit is configured to generate the original frame by encoding the encoded frame stored in the frame memory according to a request of the encoder, and the encoder is configured to perform encoding according to the original frame.

Abstract: Provided are a multi-input multi-output system which overcomes a disadvantage that optimal receiving performance cannot be maintained according to an installation environment and a performance change of a receiver when a receiving module is configured by using a fixed attenuator and a fixed phase in a line-of-sight multi-input multi-output system configuration and analogously controls an interference removing module of a receiver including a variable attenuator and a phase shifter which are controllable to enhance a receiving performance and increase frequency efficiency, in order to maximize a signal-to-interference ratio of each path and an operating method thereof.

Abstract: A semiconductor memory device includes: an enable signal generation portion suitable for generating a data output enable signal activated at a predetermined first moment corresponding to column address strobe (CAS) latency based on a read command, a strobe signal generation portion suitable for generating a data strobe signal which has a preamble section until the data output enable signal is activated from a predetermined second moment ahead of the first moment based on the read command and toggles based on a source clock during an activated section of the data output enable signal, and a data output portion suitable for outputting internal data in synchronization with the data strobe signal during the activated section of the data output enable signal.

Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.

Abstract: The present invention provides an array antenna apparatus for a rotation mode, a wireless communication terminal, and a method thereof. The apparatus according to the exemplary embodiment includes an antenna array including a plurality of antenna elements; and a control unit which determines an antenna pattern in accordance with a transmission/reception characteristic of a signal and assigns a weight to antenna elements in a position corresponding to the determined antenna pattern on the antenna array to implement a rotation mode antenna based on the antenna element to which the weight is assigned.

Abstract: The present invention relates to a reception apparatus. The reception apparatus includes a plurality of reception antennas; and a signal processing unit configured to use reception characteristic of the plurality of reception antennas, wherein the signal processing unit comprises a channel estimation unit configured to respectively estimate a channel response matrix of each signal received via the plurality of reception antennas, and a coding unit configured to define a coding matrix based on an inverse matrix of the estimated channel response matrix, and to obtain a final output signal corresponding to each reception antenna by applying the coding matrix to each received signal.

Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.