Abstract: A video on demand system for providing graceful degradation and fault tolerance comprises a plurality of media storage ends, a first level network device, and a plurality of video trunk combiners. Each of the media storage ends respectively stores a plurality of video files, and provides a plurality of frequency channels to transmit the video files. The first level network device receives each of the frequency channels provided by each of the media storage ends, and externally transmits at least one of the frequency channels provided by at least two of the media storage ends. Each of the video trunk combiners is connected between the first level network device and at least one user end, and receives the at least one of the frequency channels provided by at least two of the media storage ends via the first level network device.

Abstract: The present invention discloses a method of treating cancer in a subject. This involves co-administering a replicating virus and a matrix metalloproteinase to the subject under conditions effective to treat cancer. It also relates to a method of enhancing the delivery to and distribution within a tumor mass of therapeutic viruses. This involves co-administering a replicating virus and a matrix metalloproteinase to the tumor mass under conditions effective to enhance the delivery to and distribution within the tumor mass of therapeutic viruses. Another aspect relates to a cancer therapeutic. This involves a replicating virus and a matrix metalloproteinase.

Abstract: The present invention is directed to implantable devices (e.g., drug-delivery stents) containing nuclear receptor ligands. The nuclear receptor ligands may be, inter alia, PPAR ligands or retinoids. The invention also provides for a method of treating or preventing vascular disorders (e.g., restenosis) and related disorders using the nuclear receptor ligand-containing devices.

Abstract: An apparatus for delivering devices. The apparatus comprises a catheter with an elongated shaft having a first lumen and a second lumen extending therethrough. The apparatus further comprises a distal section with a lumen in communication with a port in a distal end of the catheter and with the first lumen and the second lumen. The first lumen is configured for a first device and the second lumen is configured for a second device to be disposed therein. The apparatus further comprises a proximal adapter coupled to the elongated shaft with a first port in communication with the first lumen and a second port in communication with the second lumen.

Abstract: The inventors have determined, contrary to the prior art and experience, how to successfully use triciribine to treat tumors and cancer by one or a combination of (i) administering triciribine only to patients which according to a diagnostic test described below, exhibit enhanced sensitivity to the drug; (ii) use of a described dosage level that minimizes the toxicity of the drug but yet still exhibits efficacy; or (iii) use of a described dosage regimen that minimizes the toxicity of the drug.

Abstract: Compositions and methods for treating cancer and proliferative angiopathies are provided. A composition can include an inhibitor of the Jak2/Stat3 signaling pathway and an inhibitor of the PI3k/Akt signaling pathway. In certain cases, the two inhibitors are capable of acting synergistically as compared to either inhibitor alone.

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract: A method for assembling a motor vehicle door includes the steps of affixing a plurality of hardware components to a secondary trim component to form a door module assembly. The door module assembly is attached to the structural door body. A trim panel is secured to the structural door body overlaying the door module assembly. The secondary trim component has a map pocket wall and the trim panel has a map pocket opening. When the trim panel overlays the secondary trim component, the trim panel cooperates with the secondary trim component to define a map pocket.

Abstract: A device and method for converting a low voltage signal into a high voltage signal are provided, which can be implemented by using a low voltage CMOS manufacturing process to convert a low voltage signal of 0V to 1.5V into a high voltage signal of 2.5V to 1.25V. According to one preferred embodiment, PMOS transistors are employed to perform voltage level conversion and supply voltages of 1.25V and 2.5V are supplied to the PMOS transistors. During the conversion, no current path exists between the supply voltages thus effectively reducing static power consumption. In addition, the low level of the high voltage signal is outputted through the drain and source of the transistor so that the low level of the high voltage signal can be accurately defined and not affected by manufacturing parameters.

Abstract: A method for assembling a motor vehicle door includes the steps of affixing a plurality of hardware components to a secondary trim component to form a door module assembly. The door module assembly is attached to the structural door body. A trim panel is secured to the structural door body overlaying the door module assembly. The secondary trim component has a map pocket wall and the trim panel has a map pocket opening. When the trim panel overlays the secondary trim component, the trim panel cooperates with the secondary trim component to define a map pocket.

Abstract: A clock circuit for supporting a plurality of memory module types is provided. The clock circuit is connected to a first type memory module slot, and a second type memory module slot. The clock circuit includes a clock generator for producing a clock signal and a clock buffer having doubly defined clock pins for outputting the first type memory clock signal or the second type memory clock signal. The clock buffer receives the clock signal and outputs a first type memory clock signal to the first type memory clock pin. The doubly defined clock pin is also capable of outputting a second type memory clock signal to the second type memory clock pin. This invention is capable of using just a single clock buffer to drive a plurality of different memory module types.

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract: A voltage level rising regulator and method for rising voltage level are implemented by a low voltage CMOS manufacturing process for converting an input voltage of 0V˜1.5V to an output voltage of 2.5V˜1.25V. According to one preferred embodiment of the invention, a 0V voltage is applied to a gate of a PMOS transistor and its source is connected to a voltage of 1.25V. As the PMOS transistor is turned on, its drain is also 1.25V that is further applied to a gate of another PMOS transistor. Then, the source of the PMOS transistor is connected to a voltage of 2.5V. As the PMOS transistor is turned on, the drain of the PMOS transistor can output an output voltage of 2.5V. When a voltage of 1.5V is applied to the regulator, and then is inverted to a voltage of 0V by an inverter. And the 0V voltage is applied to the gate of the PMOS transistor. Its source can be connected to 1.25V.

Abstract: A clock circuit for supporting a plurality of memory module types is provided. The clock circuit is connected to a first type memory module slot, and a second type memory module slot. The clock circuit includes a clock generator for producing a clock signal and a clock buffer having doubly defined clock pins for outputting the first type memory clock signal or the second type memory clock signal. The clock buffer receives the clock signal and outputs a first type memory clock signal to the first type memory clock pin. The doubly defined clock pin is also capable of outputting a second type memory clock signal to the second type memory clock pin. This invention is capable of using just a single clock buffer to drive a plurality of different memory module types.

Abstract: A noise-resistant output stage circuit with inverse-feedback control comprising two NMOS transistors. A first NMOS transistor is coupled to a first high voltage via the drain, and coupled to a first input signal via the gate. A second MOS transistor is coupled to a source of the first MOS transistor via the drain, and performing an output terminal of the output stage circuit, therewith the gate of the second MOS transistor receiving a second input signal; an alternative of the first input signal or the second input signal presents a second high voltage and the other presents a grounding, wherein the second high voltage exceeds the first high voltage. Preferably, the second high voltage is greater than twice the first high voltage. In operation, an alternative of the first NMOS transistor or the second NMOS transistor operates within a linear region.

Abstract: A high-speed and low-noise output buffer with a slew control function in coordination with a GTL+ signal specification according to the invention. In the output buffer, general and speed driving elements concurrently drives a last output element. As an input signal is changed from a first logic level to a second logic level, the general and speed driving elements simultaneously start functioning. First, the speed driving element pulls down the control voltage of the output element to a potential having a potential difference from an expected final potential. Then, the general driving element pulls down the control voltage to close to the expected final potential. The output potential of the output element changes more quickly at the beginning. When close to the expected final potential, the variation of the output potential slows down.

Abstract: A process for producing an alumina material with high strength is disclosed. The process for producing an alumina material includes the steps of (a) providing a solution containing a dispersing agent, (b) mixing a .theta.-alumina powder and an .alpha.-alumina powder with the solution to form a slurry, (c) filtering the slurry to form a green part, (d) drying the green part, and (e) densifying the dried green part to form the alumina material.

Abstract: The present invention features a direct, closed-loop method for controlling an unbalanced, power-distribution network having a great number of nodes, branches and laterals, as well as multiphase loads. The network has a radial structure. One or more formulae are first derived for a power-distribution network. The formulae may be an explicit loss formula, a voltage formula, a line flow formula or any combination thereof. Network flow programming techniques which incorporate the formulae are then developed to directly achieve steady state. Finally, the control steps are performed on the power-distribution network in real time to control its operation. The control steps may include placing a capacitor, regulator or switch at a specific position in the network and/or reconfiguring the network in some other manner.

Abstract: Synthesis of novel images from example images is achieved by interpolating among example images based on user selection of parameter values in a hierarchy of networks referred to as parent networks and child networks. Child networks describe distinct physical characteristics of the image, such as thickness of eyebrows. Parent networks describe more general or abstract characteristics related to the image, such as emotional states expressed by the image.