Abstract: A delay measurement circuit includes a transporting path selector, first and second delay measurement devices, and a controller. The delay measurement circuit forms a plurality of transporting loops through two of a first reference transporting conductive wire, a second reference transporting conductive wire, and a tested transporting conductive wire according to a control signal. The first delay measurement device respectively measures part of the transporting loops to obtain a plurality first transporting delays. The second delay measurement device respectively measures part of the transporting loops to obtain a plurality second transporting delays. The controller generates the control signal, and obtains a transporting delay of the tested transporting conductive wire according to the first transporting delays and the second transporting delays.

Abstract: A system and method for wireless wide area network (WWAN) assisted proximity wireless local area network (WLAN) peer-to-peer (P2P) connection and offloading is disclosed. The method includes the operation of identifying a first wireless device and a second wireless device between which a WLAN P2P connection is desired. Each wireless device can have a WWAN radio and a WLAN radio. WLAN information can be sent for at least one of the first and second wireless devices via the WWAN to a P2P configuration server. A WLAN P2P configuration can be received from the P2P configuration server at the first and second wireless devices via the WWAN for WLAN P2P communication between the first and second wireless devices. A WLAN P2P connection can be set up between the first and second wireless devices using the WLAN P2P configuration. The first and the second wireless devices can communicate using the WLAN P2P connection.

Abstract: A grounding grid breakpoint diagnostic method for a transient electromagnetic method, based on a transient electromagnetic detection apparatus. The method comprises: (101) disposing a test line at a position above a grounding grid to be diagnosed on the ground, and determining coordinates of a detection point; (102) obtaining information about coordinates of the detection point, and coinciding the center of the transient electromagnetic detection apparatus with the coordinates of the detection point; (103) performing, by the transient electromagnetic detection apparatus, measurement along the test line point by point, so as to obtain measurement data; (104) processing, by using diagram forming software, the measurement data to form a longitudinal resistivity cross-section diagram of the detection point according to a preset formula; (105) determining whether a breakpoint occurs at the detection point according to the longitudinal resistivity cross-section diagram.

Abstract: An article of manufacture provides a compact assembly of power amplifiers in series and in parallel. A plurality of radial power splitters and radial power combiners couple surface mounted power amplifier dice into a power platter. Thermal conduction probes chained through the power platters remove heat from the vicinity of the power amplifier dice. Surface mounted power amplifier dice may be enclosed within a matched pair of power platters. Stackable power platters may be assembled to form a 3D power amplifier pile.

Abstract: A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, ? data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<?<M.

Abstract: A method and apparatus for wireless location tracking by a wireless device. In one embodiment of the invention, the wireless device has logic to determine the information of a plurality of specific location points and to determine the location of the wireless device based on the information of the plurality of specific location points. The specific location points are selected from a target area where the wireless device is located. By selecting the specific location points in the target area, it allows hidden Access Points (APs) or Base Stations (BSs) to be detected and measured and it increases the accuracy of the tracking of the wireless device.

Abstract: The present application provides a method and a system for detecting data of an instrument.

Abstract: A user equipment (UE) is arranged to send an uplink power reference signal to an enhanced Node B (eNB) associated with multiple reception points (RPs), to receive identification of an RP set and a downlink reference signal power level, to determine a path loss estimate for each downlink reference signal received from RPs of the RP set, to determine an uplink power level that is a function of the path loss estimates determined for the downlink signals received from the RPs of the RP set, and to use the determined uplink power level during communication with the multiple RPs.

Abstract: A power amplifying apparatus is provided. The power amplifying apparatus includes a first substrate and N power amplifiers. The N power amplifiers are disposed on the first substrate, the power amplifiers respectively receives N input signals, wherein frequency bands of at least two of the inputs signals are different. And the power amplifiers respectively generate M output signals, wherein the N is a positive integer greater than 2, and M is a positive integer not equal to N.

Abstract: A water pipe wrench structure consisting of a first wrench body and a second wrench body pin jointed by a control component. The first wrench body includes an actuating piece. A tooth space is positioned on this actuating piece. This actuating piece and a tooth piece extend with a uniform curvature. The second wrench body includes a perforation to pass the control component through this perforation and the tooth space. This control component includes a column piece and a grinding tooth piece, and the grinding tooth piece can be moved by pressure, so that the grinding tooth piece can be engaged to or separated from the tooth space and thus end the movement of the control component.

Abstract: A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.

Abstract: A grounding grid breakpoint diagnostic method for a transient electromagnetic method, based on a transient electromagnetic detection apparatus. The method comprises: (101) disposing a test line at a position above a grounding grid to be diagnosed on the ground, and determining coordinates of a detection point; (102) obtaining information about coordinates of the detection point, and coinciding the center of the transient electromagnetic detection apparatus with the coordinates of the detection point; (103) performing, by the transient electromagnetic detection apparatus, measurement along the test line point by point, so as to obtain measurement data; (104) processing, by using diagram forming software, the measurement data to form a longitudinal resistivity cross-section diagram of the detection point according to a preset formula; (105) determining whether a breakpoint occurs at the detection point according to the longitudinal resistivity cross-section diagram.

Abstract: A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, p data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<?<M.

Abstract: The present disclosure provides a three-dimensional (3-D) transformer-based (TF-based) power amplifier architecture, including a power splitting plane having at least one input transformer-based circuit; and a power combining plane having at least one output transformer-based circuit. The power splitting plane includes at least one input transmission line, at least one input transformer and an input terminal. Moreover, the power combining plane includes at least one output transmission line, at least one output transformer, at least one power amplifier-cell (PA-cell) and an output terminal. The power combining plane is vertically stacked, attached and electrically connected to the power splitting plane. Consequently, as compared with the existing 2-D power amplifiers, the 3-D transformer-based power amplifier architecture of the present disclosure is capable of achieving a symmetric and compact power distribution layout.

Abstract: Uplink power control in a macro cell in a wireless network comprises transmitting a reference signal from a base station device to at least one wireless device within the macro cell. The macro cell comprises the base station device and at least one radio transmitter device that is communicatively coupled to and remote from the base station device. The base station device and one or more radio transmitter devices could be selected to be a transmission point, a reception point or a combination thereof, for each wireless device. Information relating to a transmission power of the base station device is also transmitted to the at least one wireless device. An uplink signal is received from the at least one wireless device containing information relating to an uplink power determination that is based on the reference signal and the information relating to the transmission power of the base station device.

Abstract: In accordance with some embodiments, spatial and temporal locality between threads executing on graphics processing units may be analyzed and tracked in order to improve performance. In some applications where a large number of threads are executed and those threads use common resources such as common data, affinity tracking may be used to improve performance by reducing the cache miss rate and to more effectively use relatively small-sized caches.

Abstract: A user equipment (UE) is arranged to send an uplink power reference signal to an enhanced Node B (eNB) associated with multiple reception points (RPs), to receive identification of an RP set and a downlink reference signal power level, to determine a path loss estimate for each downlink reference signal received from RPs of the RP set, to determine an uplink power level that is a function of the path loss estimates determined for the downlink signals received from the RPs of the RP set, and to use the determined uplink power level during communication with the multiple RPs.

Abstract: A half-rate clock and data recovery (CDR) circuit includes a first and a second gated voltage-controlled oscillators (GVCOs) and a first and a second frequency detectors. The first frequency detector generates a first output current according to a reference signal and a second divided clock, and the second frequency detector generates a second output current according to a first divided clock and the second divided clock. A loop filter converts either the first output current or the second output current to a first control voltage to control the second clock, and generates a second control voltage according to the first control voltage to control the first clock. A lock detector receives the reference signal and the second divided clock, and accordingly generates a lock signal.

Abstract: A half-rate clock and data recovery (CDR) circuit includes a first and a second gated voltage-controlled oscillators (GVCOs) and a first and a second frequency detectors. The first frequency detector generates a first output current according to a reference signal and a second divided clock, and the second frequency detector generates a second output current according to a first divided clock and the second divided clock. A loop filter converts either the first output current or the second output current to a first control voltage to control the second clock, and generates a second control voltage according to the first control voltage to control the first clock. A lock detector receives the reference signal and the second divided clock, and accordingly generates a lock signal.

Abstract: The present disclosure provides a three-dimensional (3-D) transformer-based (TF-based) power amplifier architecture, including a power splitting plane having at least one input transformer-based circuit; and a power combining plane having at least one output transformer-based circuit. The power splitting plane includes at least one input transmission line, at least one input transformer and an input terminal. Moreover, the power combining plane includes at least one output transmission line, at least one output transformer, at least one power amplifier-cell (PA-cell) and an output terminal. The power combining plane is vertically stacked, attached and electrically connected to the power splitting plane. Consequently, as compared with the existing 2-D power amplifiers, the 3-D transformer-based power amplifier architecture of the present disclosure is capable of achieving a symmetric and compact power distribution layout.