Abstract: A power amplifying apparatus is provided. The power amplifying apparatus includes a first substrate and N power amplifiers. The N power amplifiers are disposed on the first substrate, the power amplifiers respectively receives N input signals, wherein frequency bands of at least two of the inputs signals are different. And the power amplifiers respectively generate M output signals, wherein the N is a positive integer greater than 2, and M is a positive integer not equal to N.

Abstract: An apparatus may include a communication interface and a processor circuit. The apparatus may further include a location analyzing module operable on the processor circuit to receive a first set of location information including a first radio information item from a first radio of a first wireless terminal via the communication interface, to scan a second set of location information to identify a second radio information item matching the first radio information item, and to index the second radio information item to a location entry in the second set of location information to determine a refined location for the first wireless terminal. Other embodiments are disclosed and claimed.

Abstract: A method and a circuit for controlling an equalizer and an equalizing system are disclosed. The method includes providing a first level from a set of levels as a peaking level of the equalizer; equalizing a transmission signal by using the equalizer with the first level to obtain a first signal; providing a second level from the set of levels as the peaking level of the equalizer; equalizing the transmission signal by using the equalizer with the second level to obtain a second signal; determining a first frequency of the first signal; determining a second frequency of the second signal; comparing the first frequency and second frequency to obtain a comparing result; and determining the peaking level of the equalizer for following equalization of the transmission signal in accordance with the comparing result.

Abstract: A hybrid error correction method and a memory repair apparatus thereof are provided for a dynamic random access memory (DRAM). The memory repair apparatus includes a mode register and a hybrid error correction code and redundancy (HEAR) module. When the DRAM enters a standby mode, the mode register switches the DRAM to be controlled by the HEAR module. The HEAR module generates parity data of the error correction code within a default refresh period. The HEAR module extends the refresh period of the DRAM and uses the parity data for error detection to locate a data retention error in the DRAM until the maximum allowable refresh period supported by the HEAR module is reached. Before the DRAM returns to a working mode from a standby mode, the HEAR module performs an error correction process according to fail bit data and writes corrected data into the DRAM.

Abstract: A positioning insert for two adjacent vertebral bodies includes a plate like insert adapted to fix relative positions of the two adjacent vertebral bodies and provided with a sharp edge oppositely formed relative to the dull side and first holes defined through a side face of the plate like insert, wherein the sharp edge is formed to have an angle between 5 to 15 degrees; and an annular insert adapted to be inserted into a space between the two adjacent vertebral bodies and having second holes and a slot defined in a peripheral side face thereof to accommodate the plate like insert so as to have the plate like insert received in the slot.

Abstract: A method for identifying state of macro block of de-interlacing computing and an image processing apparatus are provided, the method is as follows. A video frame is divided into a plurality of regions, where each of the regions includes a plurality of macro blocks. Then, a basic threshold corresponding to each of the regions is provided according to a position of each of the regions in the video frame, and a first macro block is identified to be a first type macro block or a second type macro block according to the basic threshold corresponding to one of the regions where the first macro block of the macro blocks locates. Then, a corresponding de-interlacing computing step is performed on the first macro block according to an result that the first macro block is identified as the first type macro block or the second type macro block.

Abstract: Nucleic acid and polypeptide sequences corresponding to FLAT, a partly cytosolic variant of the intracellular anandamide-degrading enzyme, fatty acid amide hydrolase-1 (FAAH-1), are provided. FLAT lacks amidase activity but binds the endocannibinoid anandamide and facilitates its transport into cells. A chemical scaffold for the inhibition of anandamide transport is identified. Compositions of the invention prevent anandamide internalization in vitro, interrupt anandamide deactivation in vivo, and cause profound CB1 cannabinoid receptor-mediated analgesia in a mouse model of inflammatory pain. Accordingly, the invention also provides methods, and pharmaceutical compositions for treating conditions in which the modulation of anandamide transport would be of benefit.

Abstract: A system and method for wireless wide area network (WWAN) assisted proximity wireless local area network (WLAN) peer-to-peer (P2P) connection and offloading is disclosed. The method includes the operation of identifying a first wireless device and a second wireless device between which a WLAN P2P connection is desired. Each wireless device can have a WWAN radio and a WLAN radio. WLAN information can be sent for at least one of the first and second wireless devices via the WWAN to a P2P configuration server. A WLAN P2P configuration can be received from the P2P configuration server at the first and second wireless devices via the WWAN for WLAN P2P communication between the first and second wireless devices. A WLAN P2P connection can be set up between the first and second wireless devices using the WLAN P2P configuration. The first and the second wireless devices can communicate using the WLAN P2P connection.

Abstract: A method for identifying state of macro block of de-interlacing computing and an image processing apparatus are provided, the method is as follows. A video frame is divided into a plurality of regions, where each of the regions includes a plurality of macro blocks. Then, a basic threshold corresponding to each of the regions is provided according to a position of each of the regions in the video frame, and a first macro block is identified to be a first type macro block or a second type macro block according to the basic threshold corresponding to one of the regions where the first macro block of the macro blocks locates. Then, a corresponding de-interlacing computing step is performed on the first macro block according to an result that the first macro block is identified as the first type macro block or the second type macro block.

Abstract: A metal-oxide-metal (MOM) capacitor able to reduce area of capacitor arrays is revealed. The MOM capacitor mainly includes at least three parallel conducting layers. Each parallel conducting layer consists of a first conductive plate, a second conductive plate disposed around the first conductive plate. There is a preset distance between the first conductive plate and the second conductive plate. The first conductive plates are electrically connected by at least one first via while the second conductive plates are electrically connected by at least one second via. Thereby, while being applied to capacitor arrays, the second conductive plates of the two adjacent MOM capacitors are connected together and shared with each other, so as to significantly reduce area of the capacitor array, improve circuit density and further optimize the layout efficiency of the chip design.

Abstract: A method for operating a SAR assisted pipelined ADC includes enabling a SAR ADC in a current stage circuit for converting an input analog voltage into a digital code during a first time interval, resetting an operational amplifier of an MDAC in the current stage circuit during the first time interval, maintaining the SAR ADC of the current stage circuit in an enabled state for outputting during a second time interval, and enabling the MDAC in the current stage circuit during the second time interval. The method also includes enabling the SAR ADC in the current stage circuit for sampling during a third time interval and connecting the output terminal of the MDAC in the current stage circuit to the input terminal of the next stage circuit during the third time interval. The first, second, and third time intervals are continuous and do not overlap each other.

Abstract: A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.

Abstract: A method for operating a SAR assisted pipelined ADC includes enabling a SAR ADC in a current stage circuit for converting an input analog voltage into a digital code during a first time interval, resetting an operational amplifier of an MDAC in the current stage circuit during the first time interval, maintaining the SAR ADC of the current stage circuit in an enabled state for outputting during a second time interval, and enabling the MDAC in the current stage circuit during the second time interval. The method also includes enabling the SAR ADC in the current stage circuit for sampling during a third time interval and connecting the output terminal of the MDAC in the current stage circuit to the input terminal of the next stage circuit during the third time interval. The first, second, and third time intervals are continuous and do not overlap each other.

Abstract: A method and apparatus for wireless location tracking by a wireless device. In one embodiment of the invention, the wireless device has logic to determine the information of a plurality of specific location points and to determine the location of the wireless device based on the information of the plurality of specific location points. The specific location points are selected from a target area where the wireless device is located. By selecting the specific location points in the target area, it allows hidden Access Points (APs) or Base Stations (BSs) to be detected and measured and it increases the accuracy of the tracking of the wireless device.

Abstract: A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

Abstract: In accordance with some embodiments, spatial and temporal locality between threads executing on graphics processing units may be analyzed and tracked in order to improve performance. In some applications where a large number of threads are executed and those threads use common resources such as common data, affinity tracking may be used to improve performance by reducing the cache miss rate and to more effectively use relatively small-sized caches.

Abstract: A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

Abstract: An apparatus may include a communication interface and a processor circuit. The apparatus may further include a location analyzing module operable on the processor circuit to receive a first set of location information including a first radio information item from a first radio of a first wireless terminal via the communication interface, to scan a second set of location information to identify a second radio information item matching the first radio information item, and to index the second radio information item to a location entry in the second set of location information to determine a refined location for the first wireless terminal. Other embodiments are disclosed and claimed.

Abstract: Uplink power control in a macro cell in a wireless network comprises transmitting a reference signal from a base station device to at least one wireless device within the macro cell. The macro cell comprises the base station device and at least one radio transmitter device that is communicatively coupled to and remote from the base station device. The base station device and one or more radio transmitter devices could be selected to be a transmission point, a reception point or a combination thereof, for each wireless device. Information relating to a transmission power of the base station device is also transmitted to the at least one wireless device. An uplink signal is received from the at least one wireless device containing information relating to an uplink power determination that is based on the reference signal and the information relating to the transmission power of the base station device.

Abstract: A method for correcting a voltage offset influence of a pipelined analog to digital converter is disclosed, in which the method generates a first stage code and a first output voltage according to a first input voltage, generates a second stage code according to the first output voltage, generates a check code according to the first output voltage, determines a first correction code by referring to the first stage code and the check code, and corrects the first stage code with the first correction code when the first stage code is different from the first correction code.