Abstract: A method of generating column signals for use by a pixel array includes connecting two or more controllable bus buffers in series. The output of each of the two or more controllable bus buffers drives an associated node. The method further includes providing a column data signal to an input of the series-connected string of two or more controllable bus buffers. The method also includes sequentially enabling each controllable bus buffer in the series-connected string of two or more controllable bus buffers, such that each node is sequentially driven. Each node is electrically coupled to an input of an associated controllable local output buffer. The method further includes sequentially enabling each of the controllable local output buffers in an order associated with the sequentially enabling of the controllable bus buffers.

Abstract: A unit pixel driver circuit includes a capacitor configured to store a voltage corresponding to a desired pixel brightness and a control block. The control block may include a first, second third and fourth transistors, all of which are connected together, both in parallel and in series. The control block controls, based on the voltage stored in the capacitor, the amount of current flowing through a pixel LED. The first transistor, second transistor, third transistor and fourth transistor all share a common gate geometry size.

Abstract: A camera module is provided, comprising: a mover mounted with a lens; a stator movably supporting the mover to an optical direction of the lens; a side actuator mounted with a coil moving the mover to the optical direction relative to the stator and a magnet; a ball interposed between the mover and the stator; and rails, each rail provided at the mover and the stator to guide a linear travel of the ball, wherein the side actuator is lopsidedly arranged at each one side of the stator and the mover.

Abstract: A camera module is provided, the camera module including a mover mounted with a lens, a stator movably supporting the mover to an optical axis direction of the lens, balls interposed at one side and the other side between the mover and the stator, a ball distance maintainer constantly keeping a distance between balls to a first direction, fixation means restricting a relative movement of the mover and the stator to a first direction, and permission means allowing a relative displacement of the mover and the stator to the first direction and restricting the relative displacement of the mover and the stator to a second direction.

Abstract: A camera module is provided, the camera module including a mover mounted with a lens, a stator movably supporting the mover to an optical axis direction of the lens, and a ball interposed between the mover and the stator, wherein a first rail is provided on the mover to allow a relative movement of the ball to the mover to the optical axis direction, and a second rail is provided on the stator opposite to the first rail to allow a relative movement of the ball to the stator to the optical axis direction, and wherein the ball linearly travels along the optical axis direction when the mover and the stator relatively move.

Abstract: An air conditioning system for motor vehicles includes an air conditioner case having an external air introduction port and an internal air introduction port, an intake door rotatably installed in the air conditioner case so as to open the external air introduction port in an external air mode and open the internal air introduction port in an internal air mode, a blower configured to draw an internal air or an external air through the external air introduction port or the internal air introduction port and to blow the internal air or the external air into a vehicle room, and a control unit configured to control the intake door to move in such a direction as to close the external air introduction port and to restrain entry of rainwater into the external air introduction port, if a rotation speed level of the blower satisfies a predetermined condition in the external air mode.

Abstract: A method of driving a pixel array includes providing a ramp signal to one or more columns of the pixel array. For each cycle of the ramp signal, the method further includes providing a first row driving signal to at least a first row of the pixel array and a second row driving signal to a second row of the pixel array. A pixel array driver may include a ramp signal generator configured to produce a ramp signal, a first amplifier configured to receive the ramp signal and produce a first amplified ramp signal, and a second amplifier configured to receive the ramp signal and produce a second amplified ramp signal. The first amplified ramp signal may be electrically connected to a first set of pixels of a pixel array, and the second amplified ramp signal may be electrically connected to a second set of pixels of the pixel array.

Abstract: The present invention relates to a single cycle mixed refrigerant process for industrial cooling applications, for example, the liquefaction of natural gas. The present invention also relates to a refrigeration assembly configured to implement the processes defined herein and a mixed refrigerant composition usable in such processes.

Abstract: A unit pixel driver circuit includes a capacitor configured to store a voltage corresponding to a desired pixel brightness and a control block. The control block may include a first, second third and fourth transistors, all of which are connected together, both in parallel and in series. The control block controls, based on the voltage stored in the capacitor, the amount of current flowing through a pixel LED. The first transistor, second transistor, third transistor and fourth transistor all share a common gate geometry size.

Abstract: Embodiments provide an active matrix LED pixel driving circuit and pixel layout for increased uniform illumination of LED display panels. A plurality of sub driving transistors can be located in neighbor pixels of the pixel associated with the prime driver transistor's LED. The sub driving transistors can compensate for the process variations affecting the threshold voltage variation of the prime driver transistor resulting in uniform illumination of LED's on the display panel.

Abstract: A method of arranging components in an integrated circuit includes providing two or more circuit cells of a first type and providing two or more circuit cells of a second type. The circuit cells of the first type are configured to operate in conjunction with the circuit cells of the second type. The method further includes arranging the circuit cells of the first and second types in an alternating pattern such that each circuit cell of the first type is adjacent to at least one circuit cell of the second type. The alternating pattern may be an array of rows and columns and may include a repeating pattern of one first type cell and one second type cell in each of the columns. The alternating pattern may include a repeating pattern of one cell of the first type and two cells of the second type in each of the columns.

Abstract: A method of generating column signals for use by a pixel array includes connecting two or more controllable bus buffers in series. The output of each of the two or more controllable bus buffers drives an associated node. The method further includes providing a column data signal to an input of the series-connected string of two or more controllable bus buffers. The method also includes sequentially enabling each controllable bus buffer in the series-connected string of two or more controllable bus buffers, such that each node is sequentially driven. Each node is electrically coupled to an input of an associated controllable local output buffer. The method further includes sequentially enabling each of the controllable local output buffers in an order associated with the sequentially enabling of the controllable bus buffers.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: The present invention relates to a single cycle mixed refrigerant process for industrial cooling applications, for example, the liquefaction of natural gas. The present invention also relates to a refrigeration assembly configured to implement the processes defined herein and a mixed refrigerant composition usable in such processes.

Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.