Abstract: The present invention provides a light emitting diode (LED) driving circuit with low harmonic distortion. The LED driving circuit comprises: a rectifying circuit, a linear constant current circuit, a current limiting circuit, and a current limiting ramp slope determining circuit. The rectifying circuit is utilized for rectifying an alternating current (AC) power source to provide a direct current (DC) voltage output. The linear constant current circuit is utilized for driving at least an LED. The current limiting circuit is connected in parallel between the rectifying circuit and the linear constant current circuit, and utilized for generating a current limiting effect and determining a current limiting height. The current limiting ramp slope determining circuit is connected in parallel between the rectifying circuit and the linear constant current circuit and connected in series with the current limiting circuit, and utilized for determining a current limiting ramp slope.

Abstract: An LED driving circuit for driving an LED unit includes a power source, a detection circuit, a charging-discharging circuit, and a control circuit. The power source is coupled to the input node of the LED unit. The detection circuit is coupled to the output node of the LED unit, wherein the detection circuit is arranged to generate a detection signal according to an output signal of the LED unit. The charging-discharging circuit includes a resistive circuit, a first diode and an energy storing circuit. When a charging path is enabled, the energy storing circuit is charged by the power source. When a discharging path is enabled, the energy storing circuit is discharged to the LED unit. The control circuit is coupled to the detection circuit, the charging path and the discharging path, for selectively enabling the charging path or the discharging path according to the detection signal.

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

Abstract: The present invention provides a light emitting diode (LED) driving circuit with low harmonic distortion. The LED driving circuit comprises: a rectifying circuit, a linear constant current circuit, a current limiting circuit, and a current limiting ramp slope determining circuit. The rectifying circuit is utilized for rectifying an alternating current (AC) power source to provide a direct current (DC) voltage output. The linear constant current circuit is utilized for driving at least an LED. The current limiting circuit is connected in parallel between the rectifying circuit and the linear constant current circuit, and utilized for generating a current limiting effect and determining a current limiting height. The current limiting ramp slope determining circuit is connected in parallel between the rectifying circuit and the linear constant current circuit and connected in series with the current limiting circuit, and utilized for determining a current limiting ramp slope.

Abstract: An LED driving circuit for driving an LED unit includes a power source, a detection circuit, a charging-discharging circuit, and a control circuit. The power source is coupled to the input node of the LED unit. The detection circuit is coupled to the output node of the LED unit, wherein the detection circuit is arranged to generate a detection signal according to an output signal of the LED unit. The charging-discharging circuit includes a resistive circuit, a first diode and an energy storing circuit. When a charging path is enabled, the energy storing circuit is charged by the power source. When a discharging path is enabled, the energy storing circuit is discharged to the LED unit. The control circuit is coupled to the detection circuit, the charging path and the discharging path, for selectively enabling the charging path or the discharging path according to the detection signal.

Abstract: A light emitting diode driving circuit is provided for driving a first LED unit and a second LED unit. The light emitting diode driving circuit includes a power supply, a detection unit, a serial-parallel circuit, and a control unit. The serial-parallel circuit is coupled to the first LED unit and the second LED unit and establishes a serial connection or a parallel connection for the first LED unit and the second LED unit. The detection unit is coupled to an output end of the power supply for generating a corresponding detection signal according to an output voltage of the power supply. The control unit is arranged between the detection unit and the serial-parallel circuit. The control unit determines the first LED unit and the second LED unit to be set up in the serial connection or in the parallel connection according to the corresponding detection signal.

Abstract: A light emitting diode driving circuit is provided for driving a first LED unit and a second LED unit. The light emitting diode driving circuit includes a power supply, a detection unit, a serial-parallel circuit, and a control unit. The serial-parallel circuit is coupled to the first LED unit and the second LED unit and establishes a serial connection or a parallel connection for the first LED unit and the second LED unit. The detection unit is coupled to an output end of the power supply for generating a corresponding detection signal according to an output voltage of the power supply. The control unit is arranged between the detection unit and the serial-parallel circuit. The control unit determines the first LED unit and the second LED unit to be set up in the serial connection or in the parallel connection according to the corresponding detection signal.

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 ? thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

Abstract: A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels.

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract: There is set forth herein in one embodiment a semiconductor structure having a first region and a second region. The first region can include fins of a first fin height and the second region can include fins of a second fin height.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.

Abstract: A method includes forming a placeholder source/drain contact structure above a semiconductor material. A conformal deposition process is performed to form a liner layer above the placeholder contact structure. A dielectric layer is formed above the liner layer. A first planarization process is performed to remove material of the dielectric layer and expose a first top surface of the liner layer above the placeholder contact structure. A first cap layer is formed above the dielectric layer. A second planarization process is performed to remove material of the first cap layer and the liner layer to expose a second top surface of the placeholder contact structure. The placeholder contact structure is removed to define a source/drain contact recess in the dielectric layer. The sidewalls of the dielectric layer in the source/drain contact recess are covered by the liner layer. A conductive material is formed in the contact recess.

Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 ? thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.