Patents by Inventor Jin-Su Lee

Jin-Su Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200111660
    Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.
    Type: Application
    Filed: May 9, 2019
    Publication date: April 9, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-woon Park, Jin-su Lee, Hyung-suk Jung
  • Publication number: 20190355806
    Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.
    Type: Application
    Filed: February 12, 2019
    Publication date: November 21, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-goo KANG, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho CHO
  • Publication number: 20190129242
    Abstract: A display device including a first substrate having a first surface including a display area and a non-display area disposed outside of the display area, the display area comprising a plurality of pixels, a plurality of color filters disposed on the first surface of the first substrate, and an organic film disposed to cover the color filters. The color filters include first, second, and third color filters corresponding to the pixels and disposed in the display area, a fourth color filter disposed in the non-display area, and a fifth color filter disposed on the fourth color filter, in which at least one of the fourth and fifth color filters is spaced apart from the display area.
    Type: Application
    Filed: October 18, 2018
    Publication date: May 2, 2019
    Inventors: Sang Il PARK, Yeun Tae KIM, Min Wook PARK, Jin Su LEE, Kun Wook HAN
  • Publication number: 20190072814
    Abstract: A display device and a method for manufacturing the display device are provided. According to an exemplary embodiment, a display device includes: a first substrate on which a display area and a non-display area disposed outside the display area are defined; a second substrate facing the first substrate; a liquid crystal layer disposed between the first and second substrates; a first color filter disposed in the non-display area; a second color filter disposed on the first color filter; a first organic film disposed on the second color filter; and a seal pattern formed on the first organic film and overlapping with at least one of the first and second color filters.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 7, 2019
    Inventors: Yeun Tae KIM, Min Wook PARK, Sang II PARK, Jun Bo SIM, Jin Su LEE
  • Patent number: 9997591
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and capacitor electrically connected to the substrate. The capacitor includes a lower electrode, a dielectric layer disposed on the lower electrode, and an upper electrode disposed on the dielectric layer. The upper electrode includes a first electrode on the dielectric layer and a second electrode on the first electrode, such that the first electrode is disposed between the dielectric layer and the second electrode. The first electrode contains metal oxynitride having a formula of MxOyNz, in which an atomic ratio (y/x) of oxygen (O) to metallic element (M) is a value in the range from 0.5 to 2.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-su Lee, Gihee Cho, Dongkyun Park, Hyun-Suk Lee, Heesook Park, Jongmyeong Lee
  • Patent number: 9963783
    Abstract: A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reaction spaces, a plurality of plasma electrodes respectively disposed in the reaction spaces, a first plasma processor connected to at least two plasma electrodes, and a first plasma power source connected to the first plasma processor. The first plasma processor may include a plasma distributor or a plasma splitter.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: May 8, 2018
    Assignee: ASM GENITECH KOREA LTD.
    Inventors: Ki Jong Kim, Hyun Kyu Cho, Jin Su Lee, Se Yong Kim
  • Patent number: 9793789
    Abstract: An apparatus for protecting a grid-connected inverter from a low grid voltage includes a first output current sensor configured to sense an output current of a grid-connected inverter, a first output current calculator configured to calculate a D-axis current and a Q-axis current of the output current to obtain the output current that is sensed, and a first output current controller configured to determine whether a difference between the output current and a reference current exceeds a predetermined range, and to decrease the output current by a predetermined value when the difference between the output current and the reference current exceeds the predetermined range.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 17, 2017
    Assignee: POSCO ENERGY., LTD.
    Inventors: Jeong Heum Lee, Sang Ho Moon, Ju Young Chang, Jae Sig Kim, Jin Su Lee
  • Patent number: 9712043
    Abstract: An apparatus for controlling overcurrent of a grid-connected inverter due to an abnormal grid voltage includes a grid voltage sensor configured to sense a grid voltage according to an output current of the grid-connected inverter, a voltage variation calculator configured to calculate a D-axis voltage and a Q-axis voltage of the grid voltage to obtain variation values of the D-axis voltage and the Q-axis voltage, and an output current controller configured to determine whether at least one of the D-axis voltage variation value and the Q-axis voltage variation value exceeds a set value of the grid voltage variation, and decrease the output current by a predetermined value when one of the D-axis voltage variation value and the Q-axis voltage variation value exceeds the set value of the grid voltage variation.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: July 18, 2017
    Assignee: POSCO ENERGY CO., LTD.
    Inventors: Jeong Heum Lee, Sang Ho Moon, Ju Young Chang, Jae Sig Kim, Jin Su Lee
  • Patent number: 9673272
    Abstract: A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 6, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunjung Choi, Se Hoon Oh, Jin-Su Lee, Younsoo Kim, HanJin Lim
  • Publication number: 20170069711
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and capacitor electrically connected to the substrate. The capacitor includes a lower electrode, a dielectric layer disposed on the lower electrode, and an upper electrode disposed on the dielectric layer. The upper electrode includes a first electrode on the dielectric layer and a second electrode on the first electrode, such that the first electrode is disposed between the dielectric layer and the second electrode. The first electrode contains metal oxynitride having a formula of MxOyNz, in which an atomic ratio (y/x) of oxygen (O) to metallic element (M) is a value in the range from 0.5 to 2.
    Type: Application
    Filed: July 18, 2016
    Publication date: March 9, 2017
    Inventors: Jin-su LEE, Gihee CHO, DONGKYUN PARK, Hyun-Suk LEE, HEESOOK PARK, JONGMYEONG LEE
  • Publication number: 20160373003
    Abstract: An apparatus for protecting a grid-connected inverter from a low grid voltage includes a first output current sensor configured to sense an output current of a grid-connected inverter, a first output current calculator configured to calculate a D-axis current and a Q-axis current of the output current to obtain the output current that is sensed, and a first output current controller configured to determine whether a difference between the output current and a reference current exceeds a predetermined range, and to decrease the output current by a predetermined value when the difference between the output current and the reference current exceeds the predetermined range.
    Type: Application
    Filed: June 20, 2014
    Publication date: December 22, 2016
    Inventors: Jeong Heum LEE, Sang Ho MOON, Ju Young CHANG, Jae Sig KIM, Jin Su LEE
  • Patent number: 9524879
    Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: December 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Su Lee, Young-Wook Park, Hee-Sook Park, Dong-Bok Lee, Jong-Myeong Lee
  • Patent number: 9520460
    Abstract: A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Suk Lee, Tae-Kyun Kim, Jin-Su Lee, Dong-Kyun Park, Jong-Myeong Lee
  • Publication number: 20160258062
    Abstract: A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reaction spaces, a plurality of plasma electrodes respectively disposed in the reaction spaces, a first plasma processor connected to at least two plasma electrodes, and a first plasma power source connected to the first plasma processor. The first plasma processor may include a plasma distributor or a plasma splitter.
    Type: Application
    Filed: May 18, 2016
    Publication date: September 8, 2016
    Inventors: Ki Jong KIM, Hyun Kyu CHO, Jin Su LEE, Se Yong KIM
  • Patent number: 9371583
    Abstract: A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reaction spaces, a plurality of plasma electrodes respectively disposed in the reaction spaces, a first plasma processor connected to at least two plasma electrodes, and a first plasma power source connected to the first plasma processor. The first plasma processor may include a plasma distributor or a plasma splitter.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: June 21, 2016
    Assignee: ASM GENITECH KOREA LTD.
    Inventors: Ki Jong Kim, Hyun Kyu Cho, Jin Su Lee, Se Yong Kim
  • Publication number: 20160126828
    Abstract: An apparatus for controlling overcurrent of a grid-connected inverter due to an abnormal grid voltage includes a grid voltage sensor configured to sense a grid voltage according to an output current of the grid-connected inverter, a voltage variation calculator configured to calculate a D-axis voltage and a Q-axis voltage of the grid voltage to obtain variation values of the D-axis voltage and the Q-axis voltage, and an output current controller configured to determine whether at least one of the D-axis voltage variation value and the Q-axis voltage variation value exceeds a set value of the grid voltage variation, and decrease the output current by a predetermined value when one of the D-axis voltage variation value and the Q-axis voltage variation value exceeds the set value of the grid voltage variation.
    Type: Application
    Filed: June 20, 2014
    Publication date: May 5, 2016
    Inventors: Jeong Heum Lee, Sang Ho Moon, Ju Young Chang, Jae Sig Kim, Jin Su Lee
  • Publication number: 20160104763
    Abstract: A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.
    Type: Application
    Filed: September 24, 2015
    Publication date: April 14, 2016
    Inventors: Yunjung CHOI, Se Hoon OH, Jin-Su LEE, Younsoo KIM, HanJin LIM
  • Publication number: 20160027896
    Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.
    Type: Application
    Filed: March 26, 2015
    Publication date: January 28, 2016
    Inventors: Jin-Su LEE, Young-Wook PARK, Hee-Sook PARK, Dong-Bok LEE, Jong-Myeong LEE
  • Patent number: 9159729
    Abstract: Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: October 13, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyongsoo Kim, Jin-Su Lee, Hojun Kwon, Dongkyun Park, Jiseung Lee, Young-Seok Choi
  • Publication number: 20150249075
    Abstract: Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.
    Type: Application
    Filed: May 18, 2015
    Publication date: September 3, 2015
    Inventors: In Chul HWANG, Jae Myun KIM, Seung Jee KIM, Jin Su LEE