Abstract: Provided is a composition for forming a hard coating layer, which includes an epoxy siloxane resin, a crosslinking agent including a compound having an alicyclic epoxy group, a thermal initiator including a compound represented by Chemical Formula 2, and a photoinitiator to decrease curls and increase hardness of the hard coating film.

Abstract: Provided is a plasma etching method comprising supplying heptafluoropropyl methyl ether (HFE) gas, argon (Ar) gas and oxygen (O2) gas to a plasma chamber receiving an etching target therein, thereby to plasma-etch the etching target.

Abstract: Provided is a plasma etching method comprising supplying both hexafluoroisopropanol (HFIP) gas and argon (Ar) gas to a plasma chamber receiving an etching target therein, thereby to plasma-etch the etching target.

Abstract: A semiconductor system may include a memory controller and a non-volatile memory apparatus. The memory controller may generate a recovery command signal by measuring a power off time of the non-volatile memory apparatus. The non-volatile memory apparatus may perform a drift recovery operation based on the recovery command signal.

Abstract: A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

Abstract: A semiconductor memory apparatus includes a memory cell. The semiconductor apparatus includes a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell.

Abstract: The present invention relates to a caliper cover, and more particularly, to a caliper cover that protects a brake caliper and is firmly fixed to the brake caliper.

Abstract: A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.

Abstract: A display apparatus including a plurality of displays arranged adjacent to each other, and a connector coupled to adjacent ends of the plurality of displays to couple the plurality of displays to each other, wherein the connector electrically connects the plurality of displays.

Abstract: A sensor for measuring concentration of nitrogen oxides and detecting ammonia slip, includes an oxygen ion conductive solid electrolyte; a first electrode, contacting the solid electrolyte, reactive to nitrogen oxides; a second electrode, contacting the solid electrolyte, reactive to nitrogen oxides and separated from the first electrode; and a third electrode, contacting the solid electrolyte, reactive to ammonia, separated from the second electrode, and connected with the first electrode in parallel. The sensor also includes a power supply that supplies power between the first electrode and the third electrode connected with each other in parallel, and the second electrode. The sensor additionally includes a measuring instrument that measures an electric potential difference or an electric current between the first electrode and the third electrode connected with each other in parallel, and the second electrode.

Abstract: Various embodiments of the present invention relate to a vehicle control device and an operating method therefore. According to one embodiment, the vehicle control device includes: an open door determination unit for acquiring an open door measurement value from an on-board diagnostics (OBD) unit of a vehicle; an acceleration sensing unit for acquiring an acceleration value from the OBD unit; and a processing unit for blocking the acquired acceleration value to be transmitted from the OBD unit to an electronic control unit (ECU) and transmitting a default value of the acceleration value to the ECU, when it is determined, on the basis of the open door measurement value, that a vehicle door is open.

Abstract: A semiconductor memory apparatus includes a memory cell. The semiconductor apparatus includes a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell.

Abstract: A semiconductor device includes a memory array including a plurality of memory blocks. Each memory block includes a pipe transistor, a drain select transistor and a first memory cell connected between the pipe transistor and a bit line, and a source select transistor and a second memory cell connected between the pipe transistor and a common source line. The semiconductor device further includes an operation circuit configured to apply an operating voltage to a memory block selected to perform program and read operations, and a gate control circuit configured to control a gate of the pipe transistor included in an unselected memory block.

Abstract: There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.

Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit for performing a program operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit to perform the program operation. The control logic controls the peripheral circuit to perform a verify operation during the program operation and then apply a pre-drain select line voltage to drain select lines of the selected memory block and unselected memory blocks.

Abstract: A semiconductor device may include a first node coupled to a first pad to which a first voltage having a first voltage level is inputted; a second node coupled to a second pad to which a second voltage having a second voltage level is inputted; an internal voltage generation unit suitable for shifting a voltage level of the first node to generate an internal voltage having the second voltage level, and outputting the internal voltage to third and fourth nodes; a first internal circuit suitable for operating by employing a voltage of the second node; and a node coupling unit that electrically couples the second node to the third node during a test operation, and electrically separates the second node and the third node during a normal operation.

Abstract: There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.

Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit for performing a program operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit to perform the program operation. The control logic controls the peripheral circuit to perform a verify operation during the program operation and then apply a pre-drain select line voltage to drain select lines of the selected memory block and unselected memory blocks.

Abstract: There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.

Abstract: There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.