Patents by Inventor Jin-Wook Lee

Jin-Wook Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170040328
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Application
    Filed: October 25, 2016
    Publication date: February 9, 2017
    Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
  • RAIL TIE HAVING EMBEDDED AUTOMATIC DIFFERENTIAL SETTLEMENT COMPENSATION APPARATUS USING OIL PRESSURE FOR RAILROAD TRACKS
    Publication number: 20170009405
    Abstract: By supporting a space generated by a settlement of the track bed gravel or asphalt roadbed underneath a concrete rail tie with cylindrical rods, and installing the present invention, one each separately, on the left and right sides of the concrete rail tie, recovery from settlements is automatic, and the response to differential settlements of the left and right rails of the track due to the train load can be easily facilitated, and by installing pressure reducing valves on the upper part of the concrete rail ties, pressure can be reduced while maintaining the track system as is without having to dismantle the concrete rail ties, and accordingly the usability of the concrete rail ties can be improved.
    Type: Application
    Filed: December 4, 2014
    Publication date: January 12, 2017
    Applicant: KOREA RAILROAD RESEARCH INSTITUTE
    Inventors: Seong-Hyeok LEE, Jin-Wook LEE
  • Auxiliary device having energy harvester and electronic device including auxiliary device
    Patent number: 9520726
    Abstract: An auxiliary device including an energy harvester and an electronic device including the auxiliary device are provided. The auxiliary device includes: a housing; a storage module which is moveable within the housing; and at least one piezoelectric transducer which disposed in the housing, such that a motion of the storage module causes a deformation of the piezoelectric transducer, thus generating electric energy. An end of the piezoelectric transducer may be fixedly connected to the storage module.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: December 13, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jee-eun Yang, Jin-wook Lee, Sung-young Yun
  • SEMICONDUCTOR DEVICE HAVING STRESSOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160358925
    Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.
    Type: Application
    Filed: March 30, 2016
    Publication date: December 8, 2016
    Inventors: Keun-hee BAI, Myeong-cheol KIM, Kwan-heum LEE, Do-hyoung KIM, Jin-wook LEE, Seung-mo HA, Dong-Hoon KHANG
  • Shoe insole sensor for walk diagnosis and shoe insole flexible board combined with the same
    Patent number: 9510776
    Abstract: A shoe insole sensor includes a body including a plurality of recessed regions formed at respective locations corresponding to vertexes of N-polygon, where N is an even number, a plurality of first protrusions formed in odd recessed regions of the recessed regions, where each of the first protrusions has a first height, and a plurality of second protrusions formed in even recessed regions of the recessed regions, where each of the second protrusions has a second height different from the first height. Here, the body is formed with a nonconductive material, each of the first protrusions is formed with a conductive material, and each of the second protrusions is formed with a conductive material.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 6, 2016
    Inventor: Jin-Wook Lee
  • Integrated circuit device and method of manufacturing the same
    Patent number: 9508727
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
  • Method and apparatus for allowing playback devices to perform synchronized playback of streaming content
    Patent number: 9509635
    Abstract: An apparatus and method for allowing a plurality of playback devices to stream content of a master device simultaneously is provided. When the master device selects one of the playback devices as a reference device and multicasts a synchronization packet to the playback devices, the playback devices determine a synchronization time by comparing their own synchronization packet reception time with a synchronization packet reception time of the reference device. When the master device streams content, into which a time stamp is inserted based on the time of the reference device, the playback devices play the content based on the determined synchronization time. Therefore, even when the playback devices have different network latencies from the master device, the playback devices may accurately perform synchronized content playback.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: November 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-cheol Park, Won-joo Park, Jae-hoon Ko, Woo-jin Park, Hun-je Yeon, Jin-wook Lee
  • SEMICONDUCTOR DEVICES HAVING MULTIPLE GATE STRUCTURES AND METHODS OF MANUFACTURING SUCH DEVICES
    Publication number: 20160343858
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.
    Type: Application
    Filed: January 8, 2016
    Publication date: November 24, 2016
    Inventors: Yoon Hae KIM, Jin Wook LEE, Jong Ki JUNG, Myung II KANG, Kwang Yong YANG, Kwan Heum LEE, Byeong Chan LEE
  • LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE
    Publication number: 20160336497
    Abstract: A light emitting device having an enhanced surface property and an electrical property is provided. The light emitting device includes a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode disposed on one side of the light emitting structure and electrically connected to the first semiconductor layer, a second electrode disposed on one side of the light emitting structure and electrically connected to the second semiconductor layer, and an ohmic contact including a first layer disposed between the second electrode and the second semiconductor layer and having aluminum (Al), a second layer including at least one MxAly alloy formed by a reaction with Al included in the first layer, and a third layer disposed on the second layer and having gold (Au) is provided.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 17, 2016
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Hyun Don SONG, Ki Man KANG, Seung Hwan KIM, Sung Won David ROH, Jin Wook LEE, Eun Ju HONG, Yee Rang HONG
  • SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    Publication number: 20160329314
    Abstract: Provided are a semiconductor device and a fabricating method thereof.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 10, 2016
    Inventors: HYUN-JAE KANG, JIN-WOOK LEE, KANG-ILL SEO, YONG-MIN CHO
  • Semiconductor device including first and second trenches having substantially equal depths
    Patent number: 9484458
    Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: November 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Wook Lee, Myeong-Cheol Kim, Sang-Min Lee, Young-Ju Park, Hyung-Yong Kim, Myung-Hoon Jung
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160308012
    Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.
    Type: Application
    Filed: March 3, 2016
    Publication date: October 20, 2016
    Inventors: Jae-yeol Song, Wan-don Kim, Sang-jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung
  • SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING THE SAME
    Publication number: 20160284699
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.
    Type: Application
    Filed: January 27, 2016
    Publication date: September 29, 2016
    Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
  • Semiconductor device and fabricating method thereof
    Patent number: 9418896
    Abstract: Provided are a semiconductor device and a fabricating method thereof.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Jae Kang, Jin-Wook Lee, Kang-Ill Seo, Yong-Min Cho
  • OPERATION METHOD AND SYSTEM OF MOBILE TERMINAL
    Publication number: 20160234370
    Abstract: An operation method and mobile terminal connected to an electronic device. The operation method includes extracting a piece of content displayed on a portion of a display of the electronic device, corresponding to a user selection, from among multiple pieces of content displayed on the display; displaying a function of the mobile terminal corresponding to the extracted piece of content; and delivering, to the mobile terminal, the extracted piece of content and a command of the function of the mobile terminal that will execute the extracted piece of content.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Inventors: Hun LIM, Gene-Moo LEE, Jin-Wook LEE, Je-Hyok RYU, Woo-Jin PARK, Jin-Hyoung KIM, Shin-Il KANG
  • APPARATUS AND METHOD FOR DETECTING AND CONNECTING COUNTERPART DEVICE BY CAPTURING IMAGE OF COUNTERPART DEVICE IN WIRELESS DEVICE
    Publication number: 20160212326
    Abstract: An apparatus and a method detect and connect a counterpart device by capturing an image of the counterpart device in a wireless device. A Relative Distance Value (RDV) between the wireless device and the counterpart device is determined via image capture using a camera. The counterpart device is identified using the determined RDV.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Shin-IL Kang, Hun-Je Yeon, Jin-Wook Lee
  • INTEGRATED CIRCUIT DEVICES HAVING AIR-GAP SPACERS AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20160204262
    Abstract: Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 14, 2016
    Inventors: KANG-ILL SEO, JIN-WOOK LEE
  • SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    Publication number: 20160133522
    Abstract: Provided are a semiconductor device and a fabricating method thereof.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Hyun-Jae KANG, Jin-Wook LEE, Kang-lll SEO, Yong-Min CHO
  • INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160133632
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Application
    Filed: September 14, 2015
    Publication date: May 12, 2016
    Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
  • Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same
    Patent number: 9331072
    Abstract: Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Ill Seo, Jin-Wook Lee