Patents by Inventor Jin-Yong Oh
Jin-Yong Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240073416Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaboration Foundation, Universily-lndustry Cooperation Group of Kyung Hee UniversityInventors: Sung Chang LIM, Ha Hyun LEE, Se Yoon JEONG, Hui Yong KIM, Suk Hee CHO, Jong Ho KIM, Jin Ho LEE, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Dong Gyu SIM, Seoung Jun OH, Gwang Hoon PARK, Sea Nae PARK, Chan Woong JEON
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Patent number: 11914564Abstract: A Merkle tree-based data management method may comprise: aligning data into two-dimensional square matrix; calculating a hash value of each node of the two-dimensional square matrix; calculating hash values of each row of the two-dimensional square matrix; generating an additional column with nodes having the hash values of each row; calculating hash values of each column of the two-dimensional square matrix; generating an additional row with nodes having hash values of each column; and calculating a Merkle root by concatenating the hash values of the additional column and the hash values of the additional row.Type: GrantFiled: November 29, 2022Date of Patent: February 27, 2024Assignee: Penta Security Inc.Inventors: Jin Hyeok Oh, Keon Yun, Sun Woo Yun, Sang Min Lee, Jun Yong Lee, Sang Gyoo Sim, Tae Gyun Kim
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Patent number: 11849576Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The memory device further includes a bonding structure between the first semiconductor structure and the second semiconductor structure, the bonding structure comprising a first bonding pattern and a second bonding pattern in contact with each other, the first semiconductor structure being electrically connected with the second semiconductor structure through the bonding structure. The memory device further includes a shielding structure between the first semiconductor structure and the second semiconductor structure and surrounding the bonding structure, the shielding structure comprising a third bonding pattern and a fourth bonding pattern in contact with each other, the shielding structure being electrically connected with a biased voltage.Type: GrantFiled: January 9, 2023Date of Patent: December 19, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Jin Yong Oh
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Patent number: 11849585Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region.Type: GrantFiled: March 8, 2022Date of Patent: December 19, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Jin Yong Oh
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Patent number: 11737264Abstract: A non-volatile memory device includes a substrate, a plurality of memory blocks grouped into pages, each including an alternating layer stack on the substrate, a plurality of channel holes in the alternating layer stack, and strings of memory cells disposed along the plurality of channel holes, and at least one dummy block adjacent to the plurality of memory blocks, each including an alternating dummy layer stack having multiple conductive layers and multiple dielectric layers alternately laminated on one another on the substrate, the at least one dummy block is disposed at an outskirt of each of the pages of the plurality of memory blocks.Type: GrantFiled: January 28, 2022Date of Patent: August 22, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Jin Yong Oh
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Publication number: 20230200074Abstract: A semiconductor device includes a first substrate, a second substrate, a first connection structure, and a second connection structure. A transistor is formed in a first side of the first substrate. A doped region is formed in a first side of the second substrate. The first connection structure is formed over a second side of the second substrate, and coupled to the doped region through a first VIA that extends from the second side of the second substrate to the doped region. The second connection structure is formed over the first side of the first substrate, connected with the first connection structure via a through silicon VIA, and coupled to the transistor through a bonding VIA. The first substrate is bonded to the second substrate by the bonding VIA, with the first side of the first substrate and the first side of the second substrate being facing each other.Type: ApplicationFiled: February 22, 2023Publication date: June 22, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jin Yong OH, Youn Cheul KIM
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Publication number: 20230154548Abstract: A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.Type: ApplicationFiled: January 19, 2023Publication date: May 18, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Siyuan WANG, Jin Yong OH, Yu WANG, Ye TIAN, Zhichao DU, Xiaojiang GUO
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Patent number: 11616077Abstract: A semiconductor device includes a first substrate having a first side for forming memory cells and an opposing second side, a doped region formed in the first side of the first substrate, a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, and a transistor formed in a first side of a second substrate and coupled to the first connection structure. The first VIA extends from the second side of the first substrate to the doped region. The memory cells include a plurality of word lines formed over the first side of the first substrate, a plurality of insulating layers disposed between the plurality of word lines, and a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers.Type: GrantFiled: July 1, 2021Date of Patent: March 28, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jin Yong Oh, Youn Cheul Kim
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Patent number: 11594284Abstract: A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.Type: GrantFiled: March 25, 2021Date of Patent: February 28, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Siyuan Wang, Jin Yong Oh, Yu Wang, Ye Tian, Zhichao Du, Xiaojiang Guo
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Patent number: 11581323Abstract: A memory device includes a memory array, a circuit structure, a bonding structure between the memory array and the circuit structure, and a shielding structure between the memory array and the circuit structure and surrounding the bonding structure. The bonding structure includes a first bonding pattern and a second bonding pattern. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure includes a third bonding pattern and a fourth bonding pattern. The first bonding pattern is in contact with the second bonding pattern at a first interface between the first bonding pattern and the second bonding pattern. The third bonding pattern is in contact with the fourth bonding pattern at a second interface between the third bonding pattern and the fourth bonding pattern.Type: GrantFiled: May 18, 2021Date of Patent: February 14, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Jin Yong Oh
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Patent number: 11563029Abstract: A 3D-NAND memory includes a transistor formed in a first side of a periphery circuit substrate, a memory cell stack formed over a first side of a cell array substrate, and a first connection structure formed over an opposing second side of the cell array substrate. The memory cell stack includes a doped region formed in the first side of the cell array substrate and coupled to the first connection structure through a first VIA, a common source structure that extends from the doped region toward the first side of the periphery circuit substrate, and a second connection structure that is positioned over and coupled to the common source structure. The first side of the cell array substrate and the first side of the periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.Type: GrantFiled: May 26, 2021Date of Patent: January 24, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jin Yong Oh, Youn Cheul Kim
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Patent number: 11552089Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a first insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the first insulating structure. The 3D memory device further includes a first contact extending vertically from the second side of the substrate to be in contact with the first doped region.Type: GrantFiled: February 26, 2020Date of Patent: January 10, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Jin Yong Oh
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Patent number: 11488973Abstract: Memory device and formation method are provided. The memory device includes a substrate; a staircase structure on the substrate; a string driver structure over the staircase structure on a side opposite to the substrate; and a metal routing structure, between the string driver structure and the staircase structure along a vertical direction with respect to a lateral surface of the substrate. The staircase structure includes a plurality of word line tiers. The string driver structure includes a plurality of transistors to individually address the plurality of word line tiers. The string driver structure and the metal routing structure are vertically aligned with the staircase structure based on a lateral central region of the staircase structure.Type: GrantFiled: June 15, 2020Date of Patent: November 1, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Jin Yong Oh
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Publication number: 20220254417Abstract: A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.Type: ApplicationFiled: March 25, 2021Publication date: August 11, 2022Inventors: Siyuan WANG, Jin Yong OH, Yu WANG, Ye TIAN, Zhichao DU, Xiaojiang GUO
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Publication number: 20220189992Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region.Type: ApplicationFiled: March 8, 2022Publication date: June 16, 2022Inventor: Jin Yong Oh
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Publication number: 20220149063Abstract: A non-volatile memory device includes a substrate, a plurality of memory blocks grouped into pages, each including an alternating layer stack on the substrate, a plurality of channel holes in the alternating layer stack, and strings of memory cells disposed along the plurality of channel holes, and at least one dummy block adjacent to the plurality of memory blocks, each including an alternating dummy layer stack having multiple conductive layers and multiple dielectric layers alternately laminated on one another on the substrate, the at least one dummy block is disposed at an outskirt of each of the pages of the plurality of memory blocks.Type: ApplicationFiled: January 28, 2022Publication date: May 12, 2022Inventor: Jin Yong OH
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Three-dimensional memory devices having a backside trench isolation and methods for forming the same
Patent number: 11302711Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region.Type: GrantFiled: February 26, 2020Date of Patent: April 12, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Jin Yong Oh -
Patent number: 11282849Abstract: A non-volatile memory device includes a plurality of memory blocks and a dummy block configured to form a pool capacitor for suppressing power noise. The dummy block includes a substrate, a conductor region in the substrate, and an alternating dummy layer stack on the conductor region. The alternating dummy layer stack includes multiple conductive layers and multiple dielectric layers alternately laminated on one another.Type: GrantFiled: March 18, 2021Date of Patent: March 22, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventor: Jin Yong Oh
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Publication number: 20210366923Abstract: Memory device and formation method are provided. The memory device includes a substrate; a staircase structure on the substrate; a string driver structure over the staircase structure on a side opposite to the substrate; and a metal routing structure, between the string driver structure and the staircase structure along a vertical direction with respect to a lateral surface of the substrate. The staircase structure includes a plurality of word line tiers. The string driver structure includes a plurality of transistors to individually address the plurality of word line tiers. The string driver structure and the metal routing structure are vertically aligned with the staircase structure based on a lateral central region of the staircase structure.Type: ApplicationFiled: June 15, 2020Publication date: November 25, 2021Inventor: Jin Yong OH
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Publication number: 20210327900Abstract: A semiconductor device includes a first substrate having a first side for forming memory cells and an opposing second side, a doped region formed in the first side of the first substrate, a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, and a transistor formed in a first side of a second substrate and coupled to the first connection structure. The first VIA extends from the second side of the first substrate to the doped region. The memory cells include a plurality of word lines formed over the first side of the first substrate, a plurality of insulating layers disposed between the plurality of word lines, and a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jin Yong OH, Youn Cheul KIM