Patents by Inventor Jin-Yong Oh

Jin-Yong Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110287623
    Abstract: Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
    Type: Application
    Filed: August 3, 2011
    Publication date: November 24, 2011
    Inventors: Jin-Yong Oh, Woonkyung Lee, Jin-Sung Lee, Sunil Shim, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Jin-Soo Lim
  • Patent number: 8013389
    Abstract: Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Yong Oh, Woonkyung Lee, Jin-Sung Lee, Sunil Shim, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Jin-Soo Lim
  • Patent number: 7920021
    Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: April 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Yong Oh, Sang-youn Jo, Joon-hee Lee, Jae-sun Yun, Seong-soo Kim
  • Publication number: 20100207690
    Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.
    Type: Application
    Filed: October 16, 2009
    Publication date: August 19, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Yong Oh, Sang-youn Jo, Joon-hee Lee, Jae-sun Yun, Seong-soo Kim
  • Publication number: 20100109065
    Abstract: Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
    Type: Application
    Filed: November 4, 2009
    Publication date: May 6, 2010
    Inventors: Jin-Yong Oh, Woonkyung Lee, Jin-Sung Lee, Sunil Shim, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Jin-Soo Lim